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International Conference on Wireless Communications and Signal Processing (WCSP)

Low-Latency High-Throughput Decoder of QC-LDPC Codes by Matrix Splitting

Xinyu Zhong, Shuaicong Gong, Ming Jiang, Chunming Zhao

Published Oct 24, 2024• 2 citations
Publisher

Abstract

As the continuously increasing demand of high data rate and lower transmission, many modern communication systems employ the LDPC coding scheme with ultra-high throughput decoder to achieve these challenging requirements. However, due to the implementation complexity of decoding algorithm, designing an ultra-high throughput decoder of LDPC codes still suffers many difficulties. Therefore, we propose a FPGA-based LDPC decoder with partial parallel decoding, which splits and virtually supplements the parity-check matrix to achieve higher throughput and lower latency. Our proposed FPGA-based decoder can achieve a throughput of 6.072Gbps in 10 iterations for the highest rate 5G-LDPC code.

DOI
10.1109/wcsp62071.2024.10827659

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As the continuously increasing demand of high data rate and lower transmission, many modern communication systems employ the LDPC coding scheme with ultra-high throughput decoder to achieve these challenging requirements. However, due to the implementation complexity of decoding algorithm, designing an ultra-high throughput decoder of LDPC codes still suffers many difficulties. Therefore, we propose a FPGA-based LDPC decoder with partial parallel decoding, which splits and virtually supplements the parity-check matrix to achieve higher throughput and lower latency. Our proposed FPGA-based decoder can achieve a throughput of 6.072Gbps in 10 iterations for the highest rate 5G-LDPC code.
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