IEEE International Symposium on Circuits and Systems proceedings

A High Throughput H-QC LDPC Decoder

Yi-Hsing Chien, Mong‐Kai Ku

Published May 1, 2007• 12 citations

Abstract

In this paper, design of a high throughput low-density parity-check (LDPC) decoder using overlapped message passing scheduling algorithm is presented. Regular hierarchical quasi-cyclic (H-QC) LDPC code is used in this design to provide good coding performance at long code length. The two-level regular H-QC LDPC code matrix structure is exploited to parallelize the row and column decoding operations. Our scheduling algorithm re-arranges these operations across iteration boundaries to avoid memory access conflicts. The memory requirement is reduced by half compared to pipelined decoders without scheduling. A (12288, 6144) LDPC decoder implemented in FPGA achieves 298 Mbps throughput performance.

DOI: 10.1109/iscas.2007.378836

Related papers

Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes

Daesun Oh, Keshab K. Parhi

In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.

IEEE International Symposium on Circuits and Systems proceedingsMay 1, 200714 citations

Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes

Yongmei Dai, Zhiyuan Yan, Ning Chen

Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE.

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsApr 16, 200840 citations

Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

Zhongfeng Wang, Zhiqiang Cui

This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsJan 1, 2007155 citations

Coset-based quasi-cyclic LDPC codes for optimal overlapped message passing decoding

Yongmei Dai, Zhiyuan Yan

Due to the regular structures of quasi-cyclic (QC) low-density parity-check (LDPC) codes, the message passing decoding of these codes not only has efficient hardware implementation, but also can be overlapped to improve throughput and hardware utilization efficiency (HUE). In previous work, we proposed a scheduling scheme for the overlapped message passing (OMP) decoding of the SFT codes. In this paper, we first show that our scheduling scheme produces the minimum intra-iteration waiting time for QC LDPC codes. Then we propose a coset-based construction of QC LDPC codes, and study the girth and minimum distance properties of our new codes. Given the same parameters, the ensemble of the SFT codes is a subset of the ensemble of our coset-based QC LDPC codes. Our coset-based QC LDPC codes allow the OMP decoding to achieve greater throughput gain and higher HUE while maintaining the same theoretical performances as the SFT codes.

SiPS ... design and implementation - IEEE Workshop on Signal Processing SystemsJan 25, 20062 citations

FPGA Implementation of High-Speed LDPC Decoder with Cross-Layer Scheduling for CV-QKD

Hao Cheng, Weicheng Yu, Yong Chen +3 more

This paper addresses the high-throughput requirements of information reconciliation in continuous-variable quantum key distribution (CV-QKD) systems by proposing an FPGA-based quasi-cyclic low-density parity-check (QC-LDPC) decoder implementation utilizing cross-layer scheduling. Through a preprocessing approach involving base matrix row reordering and data merging, the scheme effectively resolves memory access conflicts in layered decoding, enabling conflict-free parallel processing. Operating at 250 MHz, the decoder achieves a throughput of 100.5 Mbps, representing a 20% improvement over conventional approaches while maintaining equivalent frame error rate performance.

International Conference on Quantum Communications, Networking, and Computing (QCNC)Apr 6, 20260 citations

Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation

Kiran Gunnam, Gwan Choi, Weihuang Wang +2 more

The implementation complexity of the decoder for low-density parity-check codes (LDPC) is dictated by memory and interconnect requirements. We propose new LDPC decoder architectures that reduce the need of message passing memory by 80% (for standard message passing)-55%(for layered decoding) and the router requirements by more than 50%. These novel architectures are based on scheduling of computation that results in "on the fly computation" of variable node and check node reliability messages. These architectures are targeted for quasi- cyclic LDPC codes such as array LDPC codes (regular QC-LDPC) and block LDPC codes (irregular QC-LDPC). FPGA and ASIC implementation results show substantial gains when compared to the existing work in the literature.

Asilomar Conference on Signals, Systems and Computers (ACSSC)Jan 1, 200626 citations