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EURASIP Journal on Advances in Signal Processing

An FPGA Implementation of"Equation missing" -Regular Low-Density Parity-Check Code Decoder

Tong Zhang, Keshab K. Parhi

Published May 20, 2003• 23 citations
Publisher

Abstract

Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed -regular LDPC code partly parallel decoder architecture based on which we implement a -bit, rate- -regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of Mbps and achieves BER at 2 dB over AWGN channel while performing maximum decoding iterations.

DOI
10.1155/s1110865703212105

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Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed -regular LDPC code partly parallel decoder architecture based on which we implement a -bit, rate- -regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of Mbps and achieves BER at 2 dB over AWGN channel while performing maximum decoding iterations.
Gallager's low-density parity-check (LDPC) codes have recently received a lot of attention because of their excellent performance. The decoder hardware implementation is obviously one of the most crucial issues determining the extent of LDPC applications in the real world. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. We propose a joint code and decoder design approach to construct a class of (3, k)-regular LDPC codes which exactly fit to a partly parallel decoder implementation. The partly parallel decoder architecture is suitable for efficient VLSI implementation and it has been shown that the jointly developed (3, k)-regular LDPC codes have very good performance.
In the past few years, Gallager's low-density parity-check (LDPC) codes received a lot of attention and many efforts have been devoted to analyzing and improving their error-correcting performance. However, little consideration has been given to the LDPC decoder VLSI implementation. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. Unfortunately, due to the randomness of LDPC codes, it is nearly impossible to develop an effective transformation for an arbitrarily given LDPC code. We propose a joint code and decoder design approach to construct a class of (3, k)-regular LDPC codes which exactly fit a partly parallel decoder implementation and have a very good performance. Moreover, for such LDPC codes, we propose a systematic, efficient encoding scheme by effectively exploiting the sparseness of its parity check matrix.
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s atEb/N0=4.25 dBE_{b}/N_{0}={\hbox {4.25~dB}}Eb​/N0​=4.25 dB(a bit error rate of10−810^{-8}10−8). It provides decoding performance within 0.5 and 0.25 dB of the floating-point sum-product algorithm with 32 and 16 iterations, respectively, and similar error-floor behavior. The decoder uses less than 40% of the lookup tables, flip-flops, and IO ports available on the FPGA device. The results provided in this paper validate the potential of stochastic LDPC decoding as a practical and competitive fully parallel decoding approach.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations
Recently, low-density parity-check (LDPC) codes have attracted much attention because of their excellent error-correcting performance and highly parallelizable decoding scheme. However, the effective VLSI implementation of an LDPC decoder remains a big challenge and is a crucial issue in determining how well we can exploit the benefits of the LDPC codes in real applications. In this paper, following the joint code and decoder design philosophy, we propose a semi-random design scheme to construct the LDPC codes that not only exhibit very good error-correcting performance but also effectively fit to partially parallel VLSI decoder implementations. The corresponding partially parallel decoder has a very regular structure and simple control mechanism. Our computer simulations show that such LDPC codes achieve very good performance comparable to their counterparts constructed in a fully random scheme, which however have little chance of fitting to partially parallel decoder implementations.