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High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm

Sun Shu long, Lin Min

Published Jan 1, 2016• 0 citations
Publisher

Abstract

Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasi-cyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.

DOI
10.1587/elex.13.20160653

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Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasi-cyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.
This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design.
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance.Although various kinds of low-complexity iterative decoding algorithms have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high complexity and long latency.In this brief, highly efficient check node processing scheme, which the processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are proposed.Compare with previous works, less than 52% could be reduced for the latency of check node unit.In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NB-QC-LDPC decoder.
Nonbinary low-density parity-check (NB-LDPC) codes constructed over GF(q) (q >; 2) can achieve higher coding gain than binary LDPC codes when the code length is moderate. A complete partial-parallel decoder architecture based on the Min-max algorithm is proposed for quasi-cyclic NB-LDPC codes in this paper. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm5) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out.
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon's limit.Nonbinary LDPC is the class of binary LDPC, which works on the higher order Galois field.The decoding performance of non-binary (NB) LDPC is better than binary LDPC for moderate code lengths.The increased computation with the increased order of field is the major challenge in hardware realization of NB-LDPC.The extension of conventional sum-product algorithm, known as extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper.However, a tradeoff exists between computational complexity and decoding performance. This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. For the first time, this paper proposes a partial-parallel decoder architecture based on the Min-max algorithm for quasi-cyclic NB-LDPC codes. A novel boundary tracking based scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In addition, layered decoding is applied, and the hardware units are optimized to reduce the latency and area. This paper also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity analysis, the proposed decoder with 5 iterations for a (837,726) code over GF(25) can easily achieve 60 Mbps throughput on ASIC devices. It is 40% more efficient than prior designs.
Short non-binary (NB) low-density parity-check (LDPC) codes provide excellent error rate performance compared to their binary counterparts. This paper presents an efficient layered decoder architecture for short high-order non-binary LDPC codes. A hardware-friendly message-adaptation extended Min-Sum (MA-EMS) algorithm is proposed, where a variety of truncation sizes and message compressions are used, such that the number of decoding cycles and the storage requirements can be reduced. A configurable design that supports a variety of truncation sizes is also proposed such that the hardware efficiency can be significantly increased. An early termination (ET) scheme is used so as to decrease the required number of decoding cycles. These techniques can greatly reduce the complexity of the decoder with almost no loss in performance. To demonstrate these techniques, a (64, 32) 256-ary LDPC decoder is implemented in a 90 nm process, which can provide a throughput of 322.9 Mbps and occupies an area of 6.74 mm2. The proposed MA-EMS decoder is able to achieve a similar error-rate performance and a much better area efficiency compared to the original EMS decoder.