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IEEE Access

An Efficient Short High-Order Non-Binary LDPC Decoder Architecture Using a Message-Adaptation EMS Algorithm

Wei-Xiang Chu, Ting-An Hu, Huang–Chang Lee, Mao-Ruei Li, Yeong-Luh Ueng

Published Jan 1, 2021• 8 citations
Publisher

Abstract

Short non-binary (NB) low-density parity-check (LDPC) codes provide excellent error rate performance compared to their binary counterparts. This paper presents an efficient layered decoder architecture for short high-order non-binary LDPC codes. A hardware-friendly message-adaptation extended Min-Sum (MA-EMS) algorithm is proposed, where a variety of truncation sizes and message compressions are used, such that the number of decoding cycles and the storage requirements can be reduced. A configurable design that supports a variety of truncation sizes is also proposed such that the hardware efficiency can be significantly increased. An early termination (ET) scheme is used so as to decrease the required number of decoding cycles. These techniques can greatly reduce the complexity of the decoder with almost no loss in performance. To demonstrate these techniques, a (64, 32) 256-ary LDPC decoder is implemented in a 90 nm process, which can provide a throughput of 322.9 Mbps and occupies an area of 6.74 mm2. The proposed MA-EMS decoder is able to achieve a similar error-rate performance and a much better area efficiency compared to the original EMS decoder.

DOI
10.1109/access.2021.3131729

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Short non-binary (NB) low-density parity-check (LDPC) codes provide excellent error rate performance compared to their binary counterparts. This paper presents an efficient layered decoder architecture for short high-order non-binary LDPC codes. A hardware-friendly message-adaptation extended Min-Sum (MA-EMS) algorithm is proposed, where a variety of truncation sizes and message compressions are used, such that the number of decoding cycles and the storage requirements can be reduced. A configurable design that supports a variety of truncation sizes is also proposed such that the hardware efficiency can be significantly increased. An early termination (ET) scheme is used so as to decrease the required number of decoding cycles. These techniques can greatly reduce the complexity of the decoder with almost no loss in performance. To demonstrate these techniques, a (64, 32) 256-ary LDPC decoder is implemented in a 90 nm process, which can provide a throughput of 322.9 Mbps and occupies an area of 6.74 mm2. The proposed MA-EMS decoder is able to achieve a similar error-rate performance and a much better area efficiency compared to the original EMS decoder.
The extended min-sum algorithm (EMS) for decoding non-binary low density parity check (NB-LDPC) codes reduces the decoding complexity by truncating the message vector by retaining only the most reliable symbols. However, the EMS algorithm does not consider that the noise of the received codeword is gradually reduced as the iteration count goes up. In this paper, we propose a low-complexity adaptive EMS algorithm, called threshold-based EMS (TB-EMS). The TB-EMS algorithm has a simple adaptive rule to calculate the new message vector length compared to the A-EMS. The proposed algorithm selects one of two message vector lengths. Experimental results show that the proposed algorithm reduces the decoding complexity with minimal performance degradation compared with the EMS algorithm. Further, the decoding performance of the TB-EMS is better than A-EMS.
The extended min-sum (EMS) algorithm is adopted for non-binary low density parity check (NB-LDPC) codes. The high complexity of EMS algorithm is a hot topic in recent years. Aiming at the problem, a low-complexity EMS algorithm based on NB-LDPC codes is proposed. Dynamic bubble-check (DBC) algorithm in elementary check node (ECN) steps is adopted to reduce the complexity of check node. Furthermore, the proposed algorithm dynamically truncates the length of the message vector by the number of decoding iterations. Taking the length of message vector truncated again as half of the original one as an example, the simulation results and complexity are analyzed. Analysis shows that, compared to the EMS algorithm, computational complexity of comparisons and real additions of check node of the proposed algorithm have reduced by about 70% and 25% respectively. Meantime, the decoding performance of the proposed algorithm approach that of EMS algorithm and the loss is only near 0.08 dB when the bit error rate (BER) is 10−3and the Galois fieldGF(q)(q=16)GF(q)(q=16)GF(q)(q=16).
Low Density Parity Check (LDPC) codes over a Galois Field GF(q) can provide significantly better error- correcting quality than binary LDPC codes with moderate code length. However, the computational complexity and memory requirement of nonbinary codes are much higher, limiting the application of non- binary LDPC codes. In this paper, we propose an adaptive message truncation algorithm for non-binary LDPC decoding, guided by the estimated code error rates. Compared to the previous fixed message truncation method, it can cut the messages adaptively, and therefore provide better decoding quality and computation complexity reduction. To further reduce the computation, we propose another adaptive check node update algorithm, simplifying the decoding by reducing the number of check nodes updating. Our simulation results demonstrate that by combining these two algorithms together, the average message size can be reduced greatly and good decoding quality is achieved, at a little cost of iterations. Compared to the existing truncation algorithms, our approach can reduce the order of complexity to O(nalog2(na)) (where nais messages size), with less performance degradation.
Non-binary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance when the code length is moderate. Previously, forward-backward schemes are used to implement check node processing, which need large memory. In this paper, a novel approach is proposed for EMS NB-LDPC decoding. Compared to EMS decoding algorithm, the message memory and the average number of iterations have been reduced. Also, the overall decoder architecture is proposed.
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon's limit.Nonbinary LDPC is the class of binary LDPC, which works on the higher order Galois field.The decoding performance of non-binary (NB) LDPC is better than binary LDPC for moderate code lengths.The increased computation with the increased order of field is the major challenge in hardware realization of NB-LDPC.The extension of conventional sum-product algorithm, known as extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper.However, a tradeoff exists between computational complexity and decoding performance. This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
This paper presents a novel truncation rule for the extended min-sum (EMS) decoding of non-binary low-density parity-check (NB-LDPC) codes. The conventional NB-LDPC decoders involve vector-messages of length equal to the field size q. The complexity of these decoders increases significantly as q increases. In the EMS algorithm, the vector-messages are truncated by discarding the less-likely symbols. In this paper, we propose a truncation rule so that the lengths of the vector-messages are reduced to the so-far best limit without compromising on the error correction capability. We devise a proximity matrix which helps to identify the essential components of a vector-message for truncation. The proposed truncation rule has been applied to several NB-LDPC codes of different field sizes. Simulation results for these codes show that the proposed rule can achieve the maximum truncation with negligible performance loss.