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arXiv:1301.2013 · IEEE Transactions on Information Forensics and Security

A Real-Time Design Based on FPGA for Expeditious Error Reconciliation in QKD System

Ke Cui, Jian Wang, Hongfei Zhang, Chun-Li Luo, Ge Jin, Teng‐Yun Chen

Published Nov 30, 2012• 25 citations
arXivHTMLPDF

Abstract

For high-speed quantum key distribution systems, error reconciliation is often the bottleneck affecting system performance. By exchanging common information through a public channel, the identical key can be generated on both communicating sides. However, the necessity to eliminate disclosed bits for security reasons lowers the final key rate. To improve this key rate, the amount of disclosed bits should be minimized. In addition, decreasing the time spent on error reconciliation also improves the key rate. In this paper, we introduce a practical method for expeditious error reconciliation implemented in a field programmable gate array for a discrete variable quantum key distribution system, and illustrate the superiority of this method to other similar algorithms running on a PC. Experimental results demonstrate the rapidity of the proposed protocol.

DOI
10.1109/tifs.2012.2228855

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For high-speed quantum key distribution systems, error reconciliation is often the bottleneck affecting system performance. By exchanging common information through a public channel, the identical key can be generated on both communicating sides. However, the necessity to eliminate disclosed bits for security reasons lowers the final key rate. To improve this key rate, the amount of disclosed bits should be minimized. In addition, decreasing the time spent on error reconciliation also improves the key rate. In this paper, we introduce a practical method for expeditious error reconciliation implemented in a field programmable gate array for a discrete variable quantum key distribution system, and illustrate the superiority of this method to other similar algorithms running on a PC. Experimental results demonstrate the rapidity of the proposed protocol.
The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process.
We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s.
In the process of quantum key distribution (QKD), error correction algorithm is used to correct the error bits of the key at both ends. The existing applied QKD system has a low key rate and is generally Kbps of magnitude. Therefore, the performance requirement of data processing such as error correction is not high. In order to cope with the development demand of high-speed QKD system in the future, this paper introduces the Winnow algorithm to realize high-speed parity and hamming error correction based on Field Programmable Gate Array (FPGA), and explores the performance limit of this algorithm. FPGA hardware implementation can achieve the scale of Mbps bandwidth, with choosing different group length of sifted key by different error rate, and can achieve higher error correction efficiency by reducing the information leakage in the process of error correction, and improves the QKD system’s secure key rate, thus helping the future high-speed QKD system.
A real-time quantum key distribution (QKD) system is developed in this paper. In the system, based on the feature of a field-programmable gate array, secure key extraction control and algorithm have been optimally designed to perform sifting, error correction, and privacy amplification altogether in real time. In the QKD experiment, information synchronization mechanism and high-speed classic data channel are designed to ensure the steady operation of the system. Decoy state and synchronous laser light source are used in the system, while the length of optical fiber between Alice and Bob is 20 km. With photons repetition frequency of 20 MHz, the final key rate could reach 17 kb/s. Smooth and robust operation is verified with 6 h continuous test and associated with encrypted voice communication test.
For continuous variable quantum key distribution (CV-QKD) protocol, information reconciliation (IR) is a key step that can significantly affect the performance of CV-QKD. Because of multidimensional reconciliation suitable for low signal-to-noise ratio (SNR) and long transmission distance scenario, a parallel architecture for the multidimensional reconciliation in CV-QKD implemented on field programmable gate array (FPGA) is proposed in this paper. Using a binarized d-dimensional spherical vector c and a parallel computation of the coefficient a and rotation matrix M, the parallel architecture achieves 45.635 Mbps processing throughput at 250 MHz in the system clock, with frame error rate (FER) less than 0.001 when the SNR exceeds 0.71 dB.
Quantum key reconciliation is an essential process of quantum key distribution (QKD). It aims to correct the transmission errors after the distribution of quantum objects over a quantum channel, where two legitimate parties use a classical public authenticated channel to disclose correlated bits for agreeing on their common key. This work proposes an alternative promising method employing LDPC-codes bit-flipping decoding to practical implementation of quantum key reconciliation. In our proposed scheme, the low-complexity code bit-flipping decoding based on syndrome decoding is modified and applied to conventional Winnow protocol to achieve both error correcting performance and low complexity of hardware realization, i.e. FPGA logic cells and/or memory. From numerical simulation while the performance of our proposed scheme in terms of final bit error rate (BER) and disclosed bits is superior to conventional Winnow and CASCADE protocols, it yields low complexity in LDPC decoding comparable to the existing LDPC-based reconciliation protocols. Therefore, the technique is promising to high-speed discrete-variable QKD applications.