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International Conference on Communication, Image and Signal Processing (CCISP)

A High-Speed FPGA Implementation of the Multidimensional Reconciliation for Continuous Variables Quantum Key Distribution

Jialu Sun, Hao Cheng, Zeyuan Jin, Yong Chen, Genlong Chen, Lihong Ren, Xueqin Jiang

Published Nov 13, 2024• 1 citation
Publisher

Abstract

For continuous variable quantum key distribution (CV-QKD) protocol, information reconciliation (IR) is a key step that can significantly affect the performance of CV-QKD. Because of multidimensional reconciliation suitable for low signal-to-noise ratio (SNR) and long transmission distance scenario, a parallel architecture for the multidimensional reconciliation in CV-QKD implemented on field programmable gate array (FPGA) is proposed in this paper. Using a binarized d-dimensional spherical vector c and a parallel computation of the coefficient a and rotation matrix M, the parallel architecture achieves 45.635 Mbps processing throughput at 250 MHz in the system clock, with frame error rate (FER) less than 0.001 when the SNR exceeds 0.71 dB.

DOI
10.1109/ccisp63826.2024.10765578

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For continuous variable quantum key distribution (CV-QKD) protocol, information reconciliation (IR) is a key step that can significantly affect the performance of CV-QKD. Because of multidimensional reconciliation suitable for low signal-to-noise ratio (SNR) and long transmission distance scenario, a parallel architecture for the multidimensional reconciliation in CV-QKD implemented on field programmable gate array (FPGA) is proposed in this paper. Using a binarized d-dimensional spherical vector c and a parallel computation of the coefficient a and rotation matrix M, the parallel architecture achieves 45.635 Mbps processing throughput at 250 MHz in the system clock, with frame error rate (FER) less than 0.001 when the SNR exceeds 0.71 dB.
In a continuous-variable quantum key distribution (CV-QKD) system, the computation speed of the post-processing procedure, including information reconciliation (IR) and privacy amplification (PA), inevitably affects the practical secret key rate. IR and PA can be implemented in parallel using low-density parity-check (LDPC) codes and hash functions, respectively. We achieve high-speed hardware-accelerated post-processing procedure for Gaussian symbols on a field-programmable gate array (FPGA) by taking advantage of its superior parallel processing ability. To this end, the sum-product algorithm decoders and a modified LDPC codes construction algorithm adapted to FPGA's characteristics are developed and employed. Two different structures including multiplexing and non-multiplexing are designed to achieve the trade-off between the speed and area of FPGAs, so that an optimal scheme can be adopted according to the requirement of a practical system. Simulation results show that the maximum throughput can reach 100 M symbols/s. We verified the correctness of the post-processing procedures when implemented on the Xilinx VC709 evaluation board, which is populated with the Virtex-7 XC7VX690T FPGA and provided some possible solutions to obtain better performance when more advanced FPGAs are available. The scheme can be applied readily for real-time key extraction and effectively reduce power consumption of the CV-QKD system.
Continuous-variable quantum key distribution (CV-QKD) requires highly efficient reconciliation techniques to operate at low signal-to-noise ratios and long distances. Multidimensional reconciliation addresses this challenge by transforming the physical Gaussian quantum channel into a virtual binary-input additive white Gaussian noise (BIAWGN) channel, enabling the use of modern errorcorrecting codes. In this work, we review the principles of multidimensional reconciliation, with a particular focus on high-dimensional constructions beyond the algebraic dimensions 1, 2, 4, 8. We describe the construction of the virtual channel, discuss practical coding schemes for reverse reconciliation, and analyse their integration with linear error-correcting codes. We also present an opensource simulation framework, HDirac, implementing multidimensional reconciliation for arbitrary dimensions, and use it to evaluate state-of-the-art LDPC codes. The results highlight key trade-offs between dimension, reconciliation efficiency, and frame error rate, providing practical guidance for CV-QKD system design.
This paper addresses the high-throughput requirements of information reconciliation in continuous-variable quantum key distribution (CV-QKD) systems by proposing an FPGA-based quasi-cyclic low-density parity-check (QC-LDPC) decoder implementation utilizing cross-layer scheduling. Through a preprocessing approach involving base matrix row reordering and data merging, the scheme effectively resolves memory access conflicts in layered decoding, enabling conflict-free parallel processing. Operating at 250 MHz, the decoder achieves a throughput of 100.5 Mbps, representing a 20% improvement over conventional approaches while maintaining equivalent frame error rate performance.
In continuous-variable (CV) quantum key distribution (QKD), the reconciliation efficiency and frame error rate of the information reconciliation have a significant impact on the secret key rate. For a fixed-rate multiedge-type low-density parity-check (LDPC) code, the reconciliation efficiency and frame error rate will inevitably vary due to the fluctuations of the signal-to-noise ratio (SNR) of the CV QKD system, which degrades the performance of the system. We propose a high-efficiency rate-adaptive information reconciliation scheme by combining raptorlike (RL) LDPC codes with the addition of trusted noises. We establish the model of adding trusted noises and combine it with the RL LDPC codes to optimize the secret key rate under the time-varying channel. The simulation results show that our scheme can maintain a high reconciliation efficiency of more than 94.4% and a low frame error rate within 15% fluctuation range of the SNR. Furthermore, we implement the hardware acceleration of the proposed rate-adaptive scheme on a graphics processing unit and achieve a decoding throughput of 65.5 Mbits/s by optimizing the storage of the parity-check matrix. Our results are useful for the practical CV QKD under the realistic time-varying channel.
Information reconciliation is a significant step for a continuous-variable quantum key distribution (CV-QKD) system. We propose a reconciliation method that allows two authorized parties to extract a consistent and secure binary key in a CV-QKD protocol, which is based on Gaussian-modulated coherent states and homodyne detection. This method named spherical reconciliation is based on spherical quantization and non-binary low-density parity-check (LDPC) codes. With the suitable signal-to-noise ratio (SNR) and code rate of non-binary LDPC codes, spherical reconciliation algorithm has a high efficiency and can extend the transmission distance of CV-QKD.
Quantum key distribution (QKD) can provide an unconditionally secure communication encryption method. Continuous-variable QKD (CVQKD) requires extracting the key from the noisy channel, leading to higher requirements for the error-correcting codes used in multidimensional reconciliation. We extend the quasi-cyclic low-density parity-check of the radio design for the global 5G mobile communication technology standard to achieve error correction under lower signal-to-noise ratio on integrated hardware. A field programmable gate array (FPGA) chip is used to realize the approximate lower triangular matrix encoding algorithm, and the core module only has the circular shift register, which reduces the encoding complexity, improves the encoding efficiency, and reduces the hardware resource consumption. For extended super-long code words, the decoding algorithm requires additional hardware resources to implement, which the previous algorithm cannot meet. Therefore, we present a hardware implementation of offset minimum sum algorithm (OMSA), which can avoid operations of complex mathematical formula. The offset factor of OMSA reduce the error caused by the low accuracy of calculation on the hardware. The update of the decoding information is layered in a partially parallel way in the matrix to achieve the cross processing of node information. It speeds up the transmission of information between different nodes and the convergence of decoding algorithm of low-complexity parallel structure. Simulation results show that the maximum theoretical coordination efficiency is 85% when the code with block length is 69632 at a bit rate of 22/68 and the signal-to-noise ratio asymptotic threshold is 0.7. Using an FPGA, ∼0.1 frame error rate was achieved, but with a zero-bit error rate, the optimal achievable secret key rate is about 200 Kbps at 30-km distance theoretically. For a 200-MHz system clock on the successfully decoded block, 125 Gbps encoding throughput and 472 Kbps decoding throughput was achieved, better than the theoretical key rate of prototype of CVQKD.