Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.Josephson tunnel junctions are the centerpiece of almost any superconducting electronic circuit, including qubits. Typically, the junctions for qubits are fabricated using shadow evaporation techniques to reduce dielectric loss contributions from the superconducting film interfaces. In recent years, however, sub-micrometer scale overlap junctions have started to attract attention. Compared to shadow mask techniques, neither an angle dependent deposition nor free-standing bridges or overlaps are needed, which are significant limitations for wafer-scale processing. This comes at the cost of breaking the vacuum during fabrication, but simplifies integration in multi-layered circuits and implementation of vastly different junction sizes and enables fabrication on a larger scale in an industrially standardized process. In this work, we demonstrate the feasibility of a subtractive process for the fabrication of overlap junctions. In an array of test contacts, we find low aging of the average normal state resistance of only 1.6% over 6 months. We evaluate the coherence properties of the junctions by employing them in superconducting transmon qubits. In time domain experiments, we find that both, the qubit life- and coherence time of our best device, are, on average, greater than 20 μs. Finally, we discuss potential improvements to our technique. This work paves the way toward a more standardized process flow with advanced materials and growth processes, and constitutes an important step for the large scale fabrication of superconducting quantum circuits.

arXiv:2006.16862Applied Physics LettersSep 21, 202034 citations

Sidewall spacer passivated epitaxial NbN/AlN/NbN Josephson junctions for superconducting qubit applications

Koki Honda, Daiki Kurihara, Hiroki Kutsuma +2 more

Epitaxial NbN/AlN/NbN Josephson junctions are promising alternatives to conventional Al/AlO $_x$ /Al junctions for superconducting qubits due to their crystalline tunnel barriers and the high transition temperature of NbN. However, their integration into quantum circuits typically requires complex fabrication processes involving amorphous interlayer dielectrics, which can degrade qubit coherence times. To address these issues, we developed sidewall spacer passivated epitaxial NbN/AlN/NbN junctions using a fabrication process that reduces both the volume of amorphous dielectric material and fabrication complexity. The fabricated junctions exhibited a large gap voltage of approximately 5.6 mV and low subgap leakage currents. By varying the thickness of the AlN tunnel barrier, high-quality junctions were fabricated over a wide range of critical current densities ${\it J}_c$ , from 0.3 to 10 $^4$ A/cm $^2$ . In addition, the comparison of the current-voltage characteristics before and after buffered hydrofluoric acid treatment indicated that the wet etching process did not degrade the electrical characteristics of the junctions. These results establish a scalable fabrication process for epitaxial Josephson junctions and provide a promising platform for high-coherence nitride-based superconducting qubits.Epitaxial NbN/AlN/NbN Josephson junctions are promising alternatives to conventional Al/AlO$_x$/Al junctions for superconducting qubits due to their crystalline tunnel barriers and the high transition temperature of NbN. However, their integration into quantum circuits typically requires complex fabrication processes involving amorphous interlayer dielectrics, which can degrade qubit coherence times. To address these issues, we developed sidewall spacer passivated epitaxial NbN/AlN/NbN junctions using a fabrication process that reduces both the volume of amorphous dielectric material and fabrication complexity. The fabricated junctions exhibited a large gap voltage of approximately 5.6 mV and low subgap leakage currents. By varying the thickness of the AlN tunnel barrier, high-quality junctions were fabricated over a wide range of critical current densities ${\it J}_c$, from 0.3 to 10$^4$ A/cm$^2$. In addition, the comparison of the current-voltage characteristics before and after buffered hydrofluoric acid treatment indicated that the wet etching process did not degrade the electrical characteristics of the junctions. These results establish a scalable fabrication process for epitaxial Josephson junctions and provide a promising platform for high-coherence nitride-based superconducting qubits.

quant-pharXiv:2610.04820Oct 6, 20260 citations

Superconducting qubit devices: fabrication suite

K. W. Chan, Tianyi Li, Wei Liu +9 more

Bulletin of the American Physical SocietyMar 6, 20200 citations

Progress and Challenges for Engineering Superconducting Qubits

William D. Oliver

Bulletin of the American Physical SocietyMar 5, 20180 citations

Schaalbare Fabricage van Supergeleidende Qubits - Een Studie van Decoherentie

Van Damme, Jacques

Quantum computing aims to leverage the principles of quantum mechanics to achieve superior information processing capabilities beyond the limits of today's computers. These machines have the potential to efficiently simulate quantum mechanical systems, revolutionizing the development of new materials, drug discovery, and fundamental physics research. Additionally, algorithms such as prime factorization and unstructured data search offer significant speed-ups on quantum computers, enhancing computational capabilities beyond current limits. The first experimental demonstrations of this central idea have sparked significant excitement and expectation in society. Superconducting circuit hardware technologies, which implement quantum computers, are rapidly maturing and transitioning from physics laboratories to industrial fabrication plants. This work aims to bridge the gap between physics laboratory fabrication techniques and industrial standards. Here, the approach starts from complementary metal-oxide-semiconductor (CMOS) compatible processes, optimized using insights from the decades of laboratory development. In particular, two alternative Josephson junction (JJ) fabrication methods are explored, the overlap junction and tri-layer junction approaches, that do not rely on the standard angled evaporation and lift-off processes. These CMOS-compatible fabrication processes are benchmarked for quality and uniformity, using superconducting resonators and qubits to probe material defects and process variability. Device metrics are used to identify and optimize the most critical fabrication steps. Using these methods, a successful overlap JJ qubit fabrication flow is demonstrated with industry standard tools on 300 mm wafer scale, achieving an initial qubit yield of 98.25%. Several devices exhibit lifetimes and coherence times exceeding 100 microseconds, comparable to state-of-the-art devices. Extensive across-wafer measurements and analysis provide insights into limiting factors such as material defects at device interfaces, identifying avenues for continued improvements. The second method, the tri-layer JJ approach, has the potential for defect-free devices with CMOS-grade uniformity by growing epitaxial junctions, patterned with advanced lithography and dry-etch techniques. However, subsequent metallization steps introduce detrimental microwave losses compromising the pristine junctions. Here, a novel tri-layer qubit design is proposed, the tri-layer merged element transmon (tri-MET), which eliminates further processing beyond pristine junction deposition and patterning. The new device is demonstrated in simulation, and initial fabrication steps are presented. In summary, this thesis presents key breakthroughs in superconducting qubit fabrication methods, providing evidence for the viability of industrial methods to fabricate high-coherence superconducting qubits. Further work will focus on addressing interface defects, improving junction uniformity, and incorporating three-dimensional integration techniques to enable large-scale quantum processors for computations beyond the classical limits.Quantum computing aims to leverage the principles of quantum mechanics to achieve superior information processing capabilities beyond the limits of today's computers. These machines have the potential to efficiently simulate quantum mechanical systems, revolutionizing the development of new materials, drug discovery, and fundamental physics research. Additionally, algorithms such as prime factorization and unstructured data search offer significant speed-ups on quantum computers, enhancing computational capabilities beyond current limits. The first experimental demonstrations of this central idea have sparked significant excitement and expectation in society. Superconducting circuit hardware technologies, which implement quantum computers, are rapidly maturing and transitioning from physics laboratories to industrial fabrication plants. This work aims to bridge the gap between physics laboratory fabrication techniques and industrial standards. Here, the approach starts from complementary metal-oxide-semiconductor (CMOS) compatible processes, optimized using insights from the decades of laboratory development. In particular, two alternative Josephson junction (JJ) fabrication methods are explored, the overlap junction and tri-layer junction approaches, that do not rely on the standard angled evaporation and lift-off processes. These CMOS-compatible fabrication processes are benchmarked for quality and uniformity, using superconducting resonators and qubits to probe material defects and process variability. Device metrics are used to identify and optimize the most critical fabrication steps. Using these methods, a successful overlap JJ qubit fabrication flow is demonstrated with industry standard tools on 300 mm wafer scale, achieving an initial qubit yield of 98.25%. Several devices exhibit lifetimes and coherence times exceeding 100 microseconds, comparable to state-of-the-art devices. Extensive across-wafer measurements and analysis provide insights into limiting factors such as material defects at device interfaces, identifying avenues for continued improvements. The second method, the tri-layer JJ approach, has the potential for defect-free devices with CMOS-grade uniformity by growing epitaxial junctions, patterned with advanced lithography and dry-etch techniques. However, subsequent metallization steps introduce detrimental microwave losses compromising the pristine junctions. Here, a novel tri-layer qubit design is proposed, the tri-layer merged element transmon (tri-MET), which eliminates further processing beyond pristine junction deposition and patterning. The new device is demonstrated in simulation, and initial fabrication steps are presented. In summary, this thesis presents key breakthroughs in superconducting qubit fabrication methods, providing evidence for the viability of industrial methods to fabricate high-coherence superconducting qubits. Further work will focus on addressing interface defects, improving junction uniformity, and incorporating three-dimensional integration techniques to enable large-scale quantum processors for computations beyond the classical limits.

May 26, 20250 citations

Fabrication Control of Superconducting Qubit Devices

Bethany M. Niedzielski

Bulletin of the American Physical SocietyMar 16, 20210 citations

Epitaxial NbN/AlN/NbN Josephson junctions are promising alternatives to conventional Al/AlO

_x

/Al junctions for superconducting qubits due to their crystalline tunnel barriers and the high transition temperature of NbN. However, their integration into quantum circuits typically requires complex fabrication processes involving amorphous interlayer dielectrics, which can degrade qubit coherence times. To address these issues, we developed sidewall spacer passivated epitaxial NbN/AlN/NbN junctions using a fabrication process that reduces both the volume of amorphous dielectric material and fabrication complexity. The fabricated junctions exhibited a large gap voltage of approximately 5.6 mV and low subgap leakage currents. By varying the thickness of the AlN tunnel barrier, high-quality junctions were fabricated over a wide range of critical current densities

{\it J}_c

, from 0.3 to 10

^4

A/cm

^2

. In addition, the comparison of the current-voltage characteristics before and after buffered hydrofluoric acid treatment indicated that the wet etching process did not degrade the electrical characteristics of the junctions. These results establish a scalable fabrication process for epitaxial Josephson junctions and provide a promising platform for high-coherence nitride-based superconducting qubits.