Development of the low power shift register memory by LR bias for the SFQ micro processor

T. Nishigai, Shohei Yamada, Nobuyuki Yoshikawa

Manami Kuniyoshi, Ken Murase, Ikki Nagaoka +4 more

Wolfgang Kassel, F.-I. Buchholz, M. Khabipov +2 more

Toshihiro Takahashi, Ryo Numaguchi, Yuki Yamanashi +1 more

We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.

Ryuta Tsutsumi, Koji Sato, Yuki Yamanashi +1 more

We propose a new inductive- and resistive- (LR) biased low-power single-flux quantum (SFQ) circuit that has a dynamic resetting mechanism of the bias current. Because the bias current returns to the initial state rapidly by switching of a Josephson junction in the bias circuit after circuit operation, the operating frequency of the LR-biased SFQ circuit can be improved. We simulated a Josephson transmission line (JTL) that employs the proposed biasing scheme and evaluated the bias current recovery time. Circuit simulation results show that the bias current recovery time of the proposed circuit is improved by 10-20% compared to that of the conventional LR-biased JTL. We have designed and measured a 10-stage JTL and an 8-bit concurrent-flow shift register (SR) with the proposed biasing scheme. We have experimentally demonstrated operation of the JTL with the bias margin of ±29.4% at the operating frequency of up to 70.4 GHz and operation of the 8-bit SR up to 12.3 GHz by the on-chip high-speed test.

H. Fujisawa, Yuto Takeshita, Kento Kato +6 more