We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.
Low-Power Single-Flux-Quantum Standard Cell Library Using 250 A/cm
2 Process for Qubit Control Applications
In this paper, we report the development of a low-power single-flux-quantum (SFQ) standard cell library and experimental results, including the cell design, high-speed test of shift-registers, delay measurement using ring oscillators, and demonstration of simple demultiplexers. We fabricated the SFQ circuits using a lowered critical current density (250 A/cm
2) process and low-voltage design (0.5 or 0.1 mV). We reduced the power consumption to 1/50 or 1/250 from the conventional SFQ circuits operating at 4.2 K. We designed several essential SFQ cells, including wiring elements, flip-flops, and logic gates with the fabrication process using four planarized Nb layers and obtained the correct operation at 0.3 K. We tested 8-bit shift-registers aiming to evaluate the operating frequency of the developed SFQ cells. The 0.1-mV shift-registers operated up to 8.5 GHz. The experimental results of ring oscillators showed good agreement with the analog circuit simulation results. We believe that our experimentally-verified standard cell library is ready to use for SFQ-based digital control of qubits, such as demultiplexing of control signals, and the timing information and power consumption will be valuable information as the baseline to discuss future scalable quantum computer systems.