LDPC convolutional codes (LDPC-CC) are a family of error-correcting codes (ECC) used in digital communication systems like the IEEE 1901 standard. High throughput and low complexity hardware architectures were designed for real time systems. In this article we demonstrate that an efficient selection of the message passing (MP) algorithm for LDPC-CC decoding improves the architecture features of related works. In fact, considering the LDPC-CC decoders proposed for the IEEE 1901 standard, we show that an appropriate Min-Sum approximation selection can significantly improve the error correction performance by 0.1 to 0.2 dB in terms of Bit Error Ratio. It can also reduce the hardware complexity by 10% to 20% with no impact on the Bit Error Ratio performance.
LDPC convolutional codes (LDPC-CC) are a family of error-correcting codes (ECC) used in digital communication systems like the IEEE 1901 standard. High throughput and low complexity hardware architectures were designed for real time systems. In this article we demonstrate that an efficient selection of the message passing (MP) algorithm for LDPC-CC decoding improves the architecture features of related works. In fact, considering the LDPC-CC decoders proposed for the IEEE 1901 standard, we show that an appropriate Min-Sum approximation selection can significantly improve the error correction performance by 0.1 to 0.2 dB in terms of Bit Error Ratio. It can also reduce the hardware complexity by 10% to 20% with no impact on the Bit Error Ratio performance.
Low-density parity-check convolutional codes (LDPC-CC) have interesting error correction features. They have a great potential to become a key error-correcting codes for enhancing reliability of modern digital communication systems, optical systems and storage devices. On the implementation side, however, the design of low-cost low-power and high-throughput LDPC-CC decoders remains challenging. This survey paper provides an overview of the state-of-the-art of different algorithmic optimizations proposed to ease and improve the LDPC-CC decoder implementations. To this end, a summary of the available decoding scheduling approaches is provided. Besides, a complexity analysis, performance comparison and an architectural analysis of LDPC-CC decoders based on different scheduling techniques is detailed.
In this paper, we propose an efficient message passing architecture for permutation matrices based LDPC code decoders. Min-sum algorithm is reformulated to facilitate significant reduction of routing complexity and memory usage. For a (2048, 1723) (6, 32) LDPC code with 4-bit quantization, 54% outgoing wires per variable node unit and 90% outgoing wires per check node unit can be saved. To further reduce hardware complexity, an optimized nonuniform quantization scheme using only 3 bits to represent each message has been investigated. The simulation result shows that it has only 0.25dB performance loss from the floating-point SPA
Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication.As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs).Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data.This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms.The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology.From the outcomes of this study, the Min-Sum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations.The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem.The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications.Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems.The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations.This positions it as a promising candidate for optimizing data communication systems.The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem.
This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in terms of complexity and hardware efficiency, of the main soft-decision and hard-decision decoding algorithms (such as Min-Sum, Optimized 2-bit Min-Sum and Reliability-based iterative Majority-Logic) are analyzed. The complexity and performance of those algorithms are improved to allow efficient hardware architectures.\n\nA new decoding algorithm called One-Minimum Min-Sum is proposed. It reduces considerably the complexity of the check node update equations of the Min-Sum algorithm. The second minimum is estimated from the first minimum value by a means of a linear approximation that allows a dynamic adjustment. The Optimized 2-bit Min-Sum algorithm is modified to initialize it with the complete LLR values and to introduce the extrinsic information in the messages sent from the variable nodes. Its variable node equation is reformulated to reduce its complexity. Both algorithms were tested for the (2048,1723) RS-based LDPC code and (16129,15372) LDPC code using an FPGA-based hardware emulator. They exhibit BER performance very close to Min-Sum algorithm and do not introduce early error-floor. \n\nIn order to show the hardware advantages of the proposed algorithms, hardware decoders were implemented in a 90 nm CMOS process and FPGA devices based on two types of architectures: full-parallel and partial-parallel one with horizontal layered schedule. The results show that the decoders are more area-time efficient than other published decoders and that the low-complexity of the Modified Optimized 2-bit Min-Sum allows the implementation of 10 Gbps decoders in current FPGA devices. \n\nFinally, a new hard-decision decoding algorithm, the Historical-Extrinsic Reliability-Based Iterative Decoder, is presented. This algorithm introduces the new idea of considering hard-decision votes as soft-decision to compute the extrinsic information of previous iterations. It is suitable for high-rate codes and improves the BER performance of the previous RBI-MLGD algorithms, with similar complexity.
The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models.
Very high data rates and decoding computational complexity place strict constraints in 5G and 6G communications. In this paper, non-uniform Quantized Decoding algorithm is proposed for Low-density Parity Check codes (LDPC). In the proposed algorithm, the check node updating process is carried out using quantization, which reduces complexity. The Sum Product Algorithm (SPA) is iterative message passing decoding techniques offer the optimal performance for LDPC codes. Implementations use message-passing decoding with more precision, results extremely high complexity. In Iterative, message-passing (MP), trapping sets and absorbing sets causes low error floor. In this article non-uniform quantization proposed to overcome dynamic range of values over uniform quantization. Simulation results provide coding gain increases closer to of 0.5 dB in higher SNR and has good error floor at 10−5.