IEEE Symposium on Computers and Communications (ISCC)

A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures

Hayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo

Published Jul 1, 2017• 8 citations

Abstract

Low-density parity-check convolutional codes (LDPC-CC) have interesting error correction features. They have a great potential to become a key error-correcting codes for enhancing reliability of modern digital communication systems, optical systems and storage devices. On the implementation side, however, the design of low-cost low-power and high-throughput LDPC-CC decoders remains challenging. This survey paper provides an overview of the state-of-the-art of different algorithmic optimizations proposed to ease and improve the LDPC-CC decoder implementations. To this end, a summary of the available decoding scheduling approaches is provided. Besides, a complexity analysis, performance comparison and an architectural analysis of LDPC-CC decoders based on different scheduling techniques is detailed.

DOI: 10.1109/iscc.2017.8024640

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