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Ingénierie des systèmes d information

Enhancing Data Communication Performance: A Comprehensive Review and Evaluation of LDPC Decoder Architectures

Maryam Imad Subhi, Qusay Al-Doori, Omar Alani

Published Oct 31, 2023• 4 citations
Publisher

Abstract

Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication.As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs).Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data.This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms.The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology.From the outcomes of this study, the Min-Sum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations.The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem.The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications.Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems.The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations.This positions it as a promising candidate for optimizing data communication systems.The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem.

DOI
10.18280/isi.280501

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Advances in Electrical and Electronic Engineering•Jun 22, 2019•5 citations
Error Correction Codes (ECCs) stand as a linchpin in ensuring data accuracy in wireless communication.As the landscape of modern communication standards continues to expand, there is a mounting inclination towards efficient ECC technologies, such as Low-Density Parity-Check codes (LDPCs).Distinguished by their near-capacity performance and low computational complexity, LDPCs are increasingly utilized in the successful encoding and decoding of data.This study undertakes an exploration of recent advancements in LDPC research, encompassing the analysis of decoding algorithms, architectures, applications, simulations, real-world implementations, and complexities across various hardware platforms.The central research problem addressed within this work is the identification of the most efficacious LDPC decoder implementation, with an emphasis placed on Field-Programmable Gate Array (FPGA) technology.From the outcomes of this study, the Min-Sum algorithm emerged as the favored choice for LDPC decoding, particularly within FPGA implementations.The selection of this algorithm is attributable to its simplicity and implementation feasibility, thus directly addressing the posed research problem.The inherent simplicity of the Min-Sum algorithm's structure renders it a practical choice for real-world applications.Further, its proficiency in error correction and compatibility with FPGA hardware underscore its potential for augmenting the reliability of data transmission in communication systems.The findings of this study advocate for the Min-Sum algorithm as a valuable asset in LDPC decoding, notably within FPGA implementations.This positions it as a promising candidate for optimizing data communication systems.The selection of FPGA as the implementation platform reaffirms its practicality and relevance in contemporary communication technology, thus offering a comprehensive solution to the identified research problem.
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The near-capacity performance and effective decoding algorithms of Low-Density Parity-Check (LDPC) codes have made them a mainstay of contemporary error correction. With an emphasis on iterative techniques like the Belief Propagation (BP) algorithm, the Min-Sum algorithm, and their variations, this paper offers a thorough analysis of decoding algorithms for LDPC codes. We investigate the trade-offs between various algorithmic techniques’ computational complexity, decoding latency, and error correction performance. Particular focus is placed on new methods and hardware-friendly algorithms that are tailored for next-generation communication systems, such 5 G and beyond.
LDPC codes improve error correction performance in soft-decision decoding by using the reliability of the received signal, offering greater accuracy than hard-decision decoding. The High Reliability Min-Max Algorithm leverages this advantage by using LLR to reduce computational complexity while improving decoding accuracy. The (837, 726) Min-Max code maintains performance similar to LDPC while being more efficient, reducing hardware resource usage and power consumption. Compared to the (4191, 3602) binary LDPC code, it offers better transmission efficiency. This paper presents the simulation results for a (512, 256) code, and the hardware implementation, using pipeline and parallel structures, highlights the high error correction capability of the proposed Min-Max code. This structure combines the error correction strengths of QC-LDPC with the simplicity of binary LDPC's hardware implementation. The proposed algorithm demonstrates similar error correction performance to LDPC codes but achieves lower complexity and higher transmission efficiency. Future research will focus on comparing the performance through ASIC implementation to further assess its effectiveness in practical systems. This comparison will offer insights into how the proposed Min-Max code can be implemented for real-world applications requiring efficient and reliable error correction performance.
5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.
Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family
The objective of this work is to propose a modified Min-Sum decoding Low Density Parity Check (LDPC) algorithm and perform the hardware implementation analysis of Min-Sum, optimized Min-Sum and modified Min-Sum decoders. The Min-Sum algorithm mainly uses the process of finding the minimum and addition. Hence the number of multiplications is drastically reduced which helps in reducing the complexity of implementation. Adding an optimisation factor to the decoder increases the accuracy and reduces the number of iterations required to compute the decoded message. Hence the process of optimisation reduces the overall decoding time required. Modified Min-Sum algorithm is proposed to further improve the performance by decreasing the number of stages in the decoding process which reduces the complexity in Field Programmable Gate Array (FPGA) implementation.