IEEE International Symposium on Circuits and Systems proceedings

Efficient Message Passing Architecture for High Throughput LDPC Decoder

Zhiqiang Cui, Zhongfeng Wang

Published May 1, 2007• 14 citations

Abstract

In this paper, we propose an efficient message passing architecture for permutation matrices based LDPC code decoders. Min-sum algorithm is reformulated to facilitate significant reduction of routing complexity and memory usage. For a (2048, 1723) (6, 32) LDPC code with 4-bit quantization, 54% outgoing wires per variable node unit and 90% outgoing wires per check node unit can be saved. To further reduce hardware complexity, an optimized nonuniform quantization scheme using only 3 bits to represent each message has been investigated. The simulation result shows that it has only 0.25dB performance loss from the floating-point SPA

DOI: 10.1109/iscas.2007.378075

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