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Proceedings of the Society Conference of IEICE

Design and evaluation of a butterfly processing unit for integer-type fast Fourier transforming using SFQ circuits

Y. Sakashita, Taiichi Kato, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Sep 3, 2013• 0 citations
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We are developing a fast Fourier transform (FFT) processor using high-speed and low-power single-flux-quantum (SFQ) circuits. Our main concern is the development of an SFQ butterfly processing circuit, which is the core processing circuit in the FFT processor. In our previous study, we have confirmed the complete operation of an integer-type butterfly processing circuit using the AIST 2.5 kA/cm2 Nb standard process at the frequency of 25 GHz. In this study, we have designed an integer-type butterfly processing circuit using the AIST 10 kA/cm2 Nb advanced process and confirmed its high-speed operation at the maximum frequency of 50 GHz.
Our aim is the development of a high-speed and low-power-dissipation fast Fourier transform processor using single-flux-quantum circuits. We have been working on the development of the core processing circuit, a butterfly processing circuit. In our previous study, we designed an integer-type butterfly processing circuit using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the local clock frequency of 50 GHz. In this study, we propose a configuration for signed-number calculation based on the two's complement conversion. We designed a butterfly processing circuit for signed numbers by using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the maximum local clock frequency of 51.6 GHz.