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Chinese Physics B

Semi-analytical model for quasi-double-layer surface electrode ion traps

Jian Zhang, Shuming Chen, Yaohua Wang

Published Nov 1, 2016• 2 citations
Publisher

Abstract

To realize scale quantum processors, the surface-electrode ion trap is an effective scaling approach, including single-layer, double-layer, and quasi-double-layer traps. To calculate critical trap parameters such as the trap center and trap depth, the finite element method (FEM) simulation was widely used, however, it is always time consuming. Moreover, the FEM simulation is also incapable of exhibiting the direct relationship between the geometry dimension and these parameters. To eliminate the problems above, House and Madsen et al. have respectively provided analytic models for single-layer traps and double-layer traps. In this paper, we propose a semi-analytical model for quasi-double-layer traps. This model can be applied to calculate the important parameters above of the ion trap in the trap design process. With this model, we can quickly and precisely find the optimum geometry design for trap electrodes in various cases.

DOI
10.1088/1674-1056/25/11/113701

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To realize scale quantum processors, the surface-electrode ion trap is an effective scaling approach, including single-layer, double-layer, and quasi-double-layer traps. To calculate critical trap parameters such as the trap center and trap depth, the finite element method (FEM) simulation was widely used, however, it is always time consuming. Moreover, the FEM simulation is also incapable of exhibiting the direct relationship between the geometry dimension and these parameters. To eliminate the problems above, House and Madsen et al. have respectively provided analytic models for single-layer traps and double-layer traps. In this paper, we propose a semi-analytical model for quasi-double-layer traps. This model can be applied to calculate the important parameters above of the ion trap in the trap design process. With this model, we can quickly and precisely find the optimum geometry design for trap electrodes in various cases.
The design of surface-electrode ion traps is studied analytically. The classical motion of a single ion in such a trap is described by coupled Mathieu equations. An analytic boundary-value solution for the Laplace equation in three dimensions with a piecewise-constant Dirichlet boundary condition is described. This solution is used to model the electrostatic potential field generated by a series of electrodes lying in a single plane. The model is applied to the problem of designing surface-electrode ion traps, including calculating important trap design parameters such as the center position of the trapped ion, trap depth, and stability parameters. The model is used to determine optimized dimensions for trap electrodes in various cases.
Surface-electrode (SE) rf traps are a promising approach to manufacturing complex ion-trap networks suitable for large-scale quantum information processing. In this paper we present analytical methods for modeling SE traps in the gapless plane approximation, and apply these methods to two particular classes of SE traps. For the SE ring trap we derive analytical expressions for the trap geometry and strength, and also calculate the depth in the absence of control fields. For translationally symmetric multipole configurations (analogs of the linear Paul trap), we derive analytical expressions for electrode geometry and strength. Further, we provide arbitrarily good approximations of the trap depth in the absence of static fields and identify the requirements for obtaining maximal depth. Lastly, we show that the depth of SE multipoles can be greatly influenced by control fields.
Ion traps can provide both physical implementation of quantum information processing and direct observation of quantum systems. Recently, surface ion traps have been developed using microfabrication technologies and are considered to be a promising platform for scalable quantum devices. This paper presents detailed guidelines for designing the electrodes of surface ion traps. First, we define and explain the key specifications including trap depth, q-parameter, secular frequency, and ion height. Then, we present a numerical-simulation-based design procedure, which involves determining the basic assumptions, determining the shape and size of the chip, designing the dimensions of the radio frequency (RF) electrode, and analyzing the direct current (DC) control voltages. As an example of this design procedure, we present a case study with tutorial-like explanations. The proposed design procedure can provide a practical guideline for designing the electrodes of surface ion traps.
We present a segmented linear surface electrode ion trap design that can be used for various applications in optical clocks and quantum computation based on trapped 171Yb+ ions. Our simulations show that calculated trap depth can reach up to several electronvolts and that the pseudopotential minimum of the trap is located above the trap surface at a distance greater than 80 μm. The described pseudopotential simulations and calculations of different trap parameters can be used to design the planar trap with required parameters. This design could be scaled to store a long chain of ions and used for quantum logic applications as well.
We investigate an effective grooved 2D ion chip design and optimize the ratio between the size of the rf electrodes and the groove. We calculate the optimal size of the groove using the analytical model, which was introduced by House, and the optimum result is obtained. We also obtain the simulated scattering points with the finite element analysis method. The analytical curve and simulated scattering points are coincident with each other. It is shown that this analytical model also fits for the grooved planar ion chip. Thus the optimum grooved 2D planar ion chip design could be obtained. It is effective for scalable quantum information processing.
The majority of microfabricated ion traps in use for quantum information processing are of the 2D 'surface-electrode' type or of the 3D 'wafer' type. Surface-electrode traps greatly simplify fabrication and hold the promise of allowing trapped-ion quantum computers to scale via standard semiconductor industry fabrication techniques. However, their geometry constrains them to having much lower trapping efficiency, depth, and harmonicity compared to 3D geometries. Conversely 3D geometries offer superior trap performance but fabrication is more complex, limiting potential to scale. We describe new 'trench' geometries that exist in the design space between these two paradigms. They still allow for a simple, planar electrode layer but with much more favourable trapping properties. We propose such traps could be 3D-printed over a 2D wafer with microfabricated components already integrated into it, thus retaining all the integration techniques and scaling advantages of surface-electrode traps. As a proof of principle we use 2-photon direct laser writing lithography to print the required electrode structures with the proposed geometry.