Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:0808.1623 · Physical Review A

Electrostatics of surface-electrode ion traps

Janus H. Wesenberg

Published Dec 5, 2008• 98 citations
arXivHTMLPDF

Abstract

Surface-electrode (SE) rf traps are a promising approach to manufacturing complex ion-trap networks suitable for large-scale quantum information processing. In this paper we present analytical methods for modeling SE traps in the gapless plane approximation, and apply these methods to two particular classes of SE traps. For the SE ring trap we derive analytical expressions for the trap geometry and strength, and also calculate the depth in the absence of control fields. For translationally symmetric multipole configurations (analogs of the linear Paul trap), we derive analytical expressions for electrode geometry and strength. Further, we provide arbitrarily good approximations of the trap depth in the absence of static fields and identify the requirements for obtaining maximal depth. Lastly, we show that the depth of SE multipoles can be greatly influenced by control fields.

DOI
10.1103/physreva.78.063410

Related papers

Analytic model for electrostatic fields in surface-electrode ion traps

Matthew Gregory House

The design of surface-electrode ion traps is studied analytically. The classical motion of a single ion in such a trap is described by coupled Mathieu equations. An analytic boundary-value solution for the Laplace equation in three dimensions with a piecewise-constant Dirichlet boundary condition is described. This solution is used to model the electrostatic potential field generated by a series of electrodes lying in a single plane. The model is applied to the problem of designing surface-electrode ion traps, including calculating important trap design parameters such as the center position of the trapped ion, trap depth, and stability parameters. The model is used to determine optimized dimensions for trap electrodes in various cases.

Physical Review A•Sep 2, 2008•120 citations

The Effect of Trap Design on the Scalability of Trapped-Ion Quantum Technologies

Le Minh Anh Nguyen, Brant Bowers, Sara Mouradian

To increase the power of a trapped-ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field, which, in turn, depends on the electrode geometry. Here, we consider how the electrode geometry affects the following radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards the integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.

arXiv:2503.00218•Entropy•May 29, 2025•3 citations

Surface-electrode architecture for ion-trap quantum information processing

John Chiaverini, R. B. Blakestad, J. Britton +5 more

We investigate a surface-mounted electrode geometry for miniature linear radio frequency Paul ion traps. The electrodes reside in a single plane on a substrate, and the pseudopotential minimum of the trap is located above the substrate at a distance on order of the electrodes' lateral extent or separation. This architecture provides the possibility to apply standard microfabrication principles to the construction of multiplexed ion traps, which may be of particular importance in light of recent proposals for large-scale quantum computation based on individual trapped ions.

Quantum Information and Computation•Sep 1, 2005•195 citations

Surface-electrode architecture for ion-trap quantum information processing

John Chiaverini, R. B. Blakestad, J. Britton +5 more

We investigate a surface-mounted electrode geometry for miniature linear radio frequency Paul ion traps. The electrodes reside in a single plane on a substrate, and the pseudopotential minimum of the trap is located above the substrate at a distance on the order of the electrodes' lateral extent or separation. This architecture provides the possibility to apply standard microfabrication principles to the construction of multiplexed ion traps, which may be of particular importance in light of recent proposals for large-scale quantum computation based on individual trapped ions.

Quantum Information and Computation•Sep 1, 2005•145 citations

Semi-analytical model for quasi-double-layer surface electrode ion traps

Jian Zhang, Shuming Chen, Yaohua Wang

To realize scale quantum processors, the surface-electrode ion trap is an effective scaling approach, including single-layer, double-layer, and quasi-double-layer traps. To calculate critical trap parameters such as the trap center and trap depth, the finite element method (FEM) simulation was widely used, however, it is always time consuming. Moreover, the FEM simulation is also incapable of exhibiting the direct relationship between the geometry dimension and these parameters. To eliminate the problems above, House and Madsen et al. have respectively provided analytic models for single-layer traps and double-layer traps. In this paper, we propose a semi-analytical model for quasi-double-layer traps. This model can be applied to calculate the important parameters above of the ion trap in the trap design process. With this model, we can quickly and precisely find the optimum geometry design for trap electrodes in various cases.

Chinese Physics B•Nov 1, 2016•2 citations

Surface Planar Ion Chip for Linear Radio-Frequency Paul Traps

Jinyin Wan, Qu Qiu-Zhi, Zichao Zhou +3 more

We propose a surface planar ion chip which forms a linear radio frequency Paul ion trap. The electrodes reside in the two planes of a chip, and the trap axis is located above the chip surface. Its electric field and potential distribution are similar to the standard linear radio frequency Paul ion trap. This ion trap geometry may be greatly meaningful for quantum information processing.

Chinese Physics Letters•May 1, 2007•4 citations
Surface-electrode (SE) rf traps are a promising approach to manufacturing complex ion-trap networks suitable for large-scale quantum information processing. In this paper we present analytical methods for modeling SE traps in the gapless plane approximation, and apply these methods to two particular classes of SE traps. For the SE ring trap we derive analytical expressions for the trap geometry and strength, and also calculate the depth in the absence of control fields. For translationally symmetric multipole configurations (analogs of the linear Paul trap), we derive analytical expressions for electrode geometry and strength. Further, we provide arbitrarily good approximations of the trap depth in the absence of static fields and identify the requirements for obtaining maximal depth. Lastly, we show that the depth of SE multipoles can be greatly influenced by control fields.
The design of surface-electrode ion traps is studied analytically. The classical motion of a single ion in such a trap is described by coupled Mathieu equations. An analytic boundary-value solution for the Laplace equation in three dimensions with a piecewise-constant Dirichlet boundary condition is described. This solution is used to model the electrostatic potential field generated by a series of electrodes lying in a single plane. The model is applied to the problem of designing surface-electrode ion traps, including calculating important trap design parameters such as the center position of the trapped ion, trap depth, and stability parameters. The model is used to determine optimized dimensions for trap electrodes in various cases.
To increase the power of a trapped-ion quantum information processor, the qubit number, gate speed, and gate fidelity must all increase. All three of these parameters are influenced by the trapping field, which, in turn, depends on the electrode geometry. Here, we consider how the electrode geometry affects the following radial trapping parameters: trap height, harmonicity, depth, and trap frequency. We introduce a simple multi-wafer geometry comprising a ground plane above a surface trap and compare the performance of this trap to a surface trap and a multi-wafer trap that is a miniaturized version of a linear Paul trap. We compare the voltage and frequency requirements needed to reach a desired radial trap frequency and find that the two multi-wafer trap designs provide significant improvements in expected power dissipation over the surface trap design in large part due to increased harmonicity. Finally, we consider the fabrication requirements and the path towards the integration of the necessary optical control. This work provides a basis to optimize future trap designs with scalability in mind.
We investigate a surface-mounted electrode geometry for miniature linear radio frequency Paul ion traps. The electrodes reside in a single plane on a substrate, and the pseudopotential minimum of the trap is located above the substrate at a distance on order of the electrodes' lateral extent or separation. This architecture provides the possibility to apply standard microfabrication principles to the construction of multiplexed ion traps, which may be of particular importance in light of recent proposals for large-scale quantum computation based on individual trapped ions.
We investigate a surface-mounted electrode geometry for miniature linear radio frequency Paul ion traps. The electrodes reside in a single plane on a substrate, and the pseudopotential minimum of the trap is located above the substrate at a distance on the order of the electrodes' lateral extent or separation. This architecture provides the possibility to apply standard microfabrication principles to the construction of multiplexed ion traps, which may be of particular importance in light of recent proposals for large-scale quantum computation based on individual trapped ions.
To realize scale quantum processors, the surface-electrode ion trap is an effective scaling approach, including single-layer, double-layer, and quasi-double-layer traps. To calculate critical trap parameters such as the trap center and trap depth, the finite element method (FEM) simulation was widely used, however, it is always time consuming. Moreover, the FEM simulation is also incapable of exhibiting the direct relationship between the geometry dimension and these parameters. To eliminate the problems above, House and Madsen et al. have respectively provided analytic models for single-layer traps and double-layer traps. In this paper, we propose a semi-analytical model for quasi-double-layer traps. This model can be applied to calculate the important parameters above of the ion trap in the trap design process. With this model, we can quickly and precisely find the optimum geometry design for trap electrodes in various cases.