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Asilomar Conference on Signals, Systems and Computers (ACSSC)

A solution for memory collision in semi-parallel FPGA-based LDPC decoder design

Radivoje Zarubica, Stephen G. Wilson

Published Nov 1, 2007• 7 citations
Publisher

Abstract

Low Density Parity Check (LDPC) decoders implementing long blocklength codes require semi-parallel design. One challenge when implementing these codes on Field Programmable Gate Arrays (FPGAs) is efficiently storing messages needed in the iteration process. To meet this challenge, a new class of LDPC codes is presented. They combine regularity of implementation with reduction of time needed for decoding process, and do not suffer of any significant performance loss due to their structure.

DOI
10.1109/acssc.2007.4487366

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Low Density Parity Check (LDPC) decoders implementing long blocklength codes require semi-parallel design. One challenge when implementing these codes on Field Programmable Gate Arrays (FPGAs) is efficiently storing messages needed in the iteration process. To meet this challenge, a new class of LDPC codes is presented. They combine regularity of implementation with reduction of time needed for decoding process, and do not suffer of any significant performance loss due to their structure.
LowDensity Parity Check(LDPC)decoders imple- menting longblocklength codesrequire semi-parallel design. One challenge whenimplementing these codes onField Programmable GateArrays(FPGAs)isefficiently storing messages neededin theiteration process. Tomeetthis challenge, anewclass ofLDPC codesispresented. Theycombineregularity ofimplementation withreduction oftimeneededfordecoding process, anddonot suffer ofanysignificant performance loss duetotheir structure. I.INTRODUCTION Lowdensity parity check(LDPC)codes havegarnered a great deal ofattention intheerror control coding field recently, duetotheability toimplement soft-decision decoders that perform veryneartheShannon bound(for longblocklengths). Thedecoding algorithm isiterative, using message passing amongnodes inaTanner graph representation ofthecode, and allows parallel, orsemi-parallel processing inthecomputation tospeed decoding.
Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed -regular LDPC code partly parallel decoder architecture based on which we implement a -bit, rate- -regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of Mbps and achieves BER at 2 dB over AWGN channel while performing maximum decoding iterations.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations
In recent years, the amount of digital data which is stored and transmitted for private and public usage has increased considerably. To allow a save transmission and storage of data despite of error-prone transmission media, error correcting codes are used. A large variety of codes has been developed, and in the past decade low-density parity-check (LDPC) codes which have an excellent error correction performance became more and more popular. Today, low-density parity-check codes have been adopted for several standards, and efficient decoder hardware architectures are known for the chosen structured codes. However, the existing decoder designs lack flexibility as only few structured codes can be decoded with one decoder chip. In consequence, different codes require a redesign of the decoder, and few solutions exist for decoding of codes which are not quasi-cyclic or which are unstructured. In this thesis, three different approaches are presented for the implementation of fully programmable LDPC decoders which can decode arbitrary LDPC codes. As a design study, the first programmable decoder which uses a heuristic mapping algorithm is realized on a field-programmable gate array (FPGA), and error correction curves are measured to verify the correct functionality. The main contribution of this thesis lies in the development of the second and the third architecture and an appropriate mapping algorithm. The proposed fully programmable decoder architectures use one-phase message passing and layered decoding and can decode arbitrary LDPC codes using an optimum mapping and scheduling algorithm. The presented programmable architectures are in fact generalized decoder architectures from which the known decoder architectures for structured LDPC codes can be derived.
Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and graphics processing units (GPU) based systems, and highlights the current challenges that still have to be overcome on the path to more efficient NB-LDPC decoder architectures.
In this paper, design of a high throughput low-density parity-check (LDPC) decoder using overlapped message passing scheduling algorithm is presented. Regular hierarchical quasi-cyclic (H-QC) LDPC code is used in this design to provide good coding performance at long code length. The two-level regular H-QC LDPC code matrix structure is exploited to parallelize the row and column decoding operations. Our scheduling algorithm re-arranges these operations across iteration boundaries to avoid memory access conflicts. The memory requirement is reduced by half compared to pipelined decoders without scheduling. A (12288, 6144) LDPC decoder implemented in FPGA achieves 298 Mbps throughput performance.