FPGA-based LDPC decoder design

Radivoje Zarubica

Published Jan 1, 2007• 0 citations

Abstract

LowDensity Parity Check(LDPC)decoders imple- menting longblocklength codesrequire semi-parallel design. One challenge whenimplementing these codes onField Programmable GateArrays(FPGAs)isefficiently storing messages neededin theiteration process. Tomeetthis challenge, anewclass ofLDPC codesispresented. Theycombineregularity ofimplementation withreduction oftimeneededfordecoding process, anddonot suffer ofanysignificant performance loss duetotheir structure. I.INTRODUCTION Lowdensity parity check(LDPC)codes havegarnered a great deal ofattention intheerror control coding field recently, duetotheability toimplement soft-decision decoders that perform veryneartheShannon bound(for longblocklengths). Thedecoding algorithm isiterative, using message passing amongnodes inaTanner graph representation ofthecode, and allows parallel, orsemi-parallel processing inthecomputation tospeed decoding.

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