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IET Communications

Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders

Leonardo J. Arnone, J. Castiñeira Moreira, Patrick Guy Farrell

Published Aug 14, 2012• 5 citations
Publisher

Abstract

Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.

DOI
10.1049/iet-com.2011.0767

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•Jul 9, 2013•0 citations
Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.
Low-Density Parity-Check (LDPC) codes are very efficient error control codes that are being considered as part of many next generation communication systems. In this paper FPGA implementations of two low complexity decoders are presented. These two implementations operate over any kind of parity check matrix, (including those randomly generated, structurally generated, either systematic or non systematic) and can be parametrically performed for any code rate k/n. The proposed implementations are both of very low complexity, because they operate using only sums, subtracts and look-up tables. One of these decoders offers the advantage of not requiring the knowledge of the signal-to-noise ratio of the channel, as it usually happens to most of decoders for LDPC codes.
A new soft-input,soft-output algorithm for decoding LDPC codes is described in this paper.Using soft squared Euclidean distance as the metric,the algorithm realizes decoding by iterating the antilog-sum of the Euclidean distance.A simplified algorithm is also put forward to reduce computational complexity.The proposed algorithm does not require knowledge of the signal-to-noise ratio of the received signal and is less complex to implement than other soft decision algorithms.The results of simulation show that the performance is very close to that of sum-product algorithm while the computational complexity is sharply reduced.
Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput.
With the superior error correction capability, low-density parity-check (LDPC) codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. In the past, various structures of single code-rate LDPC decoders have been reported. However, to cover a wide range of service requirements and diverse interference conditions in wireless applications, LDPC decoders that can operate at both high and low code rates are desirable. In this paper, a 9-k code length multi-rate LDPC decoder architecture is presented and implemented on a Xilinx field-programmable gate array device. Using pin selection, three operating modes, namely, the irregular 1/2 code mode, the regular 5/8 code mode, and the regular 7/8 code mode, are supported. Furthermore, to suppress the error floor level, a characterization on the conditions for short cycles in a LDPC code matrix expanded from a small base matrix is presented, and a cycle elimination algorithm is developed to detect and break such short cycles. The effectiveness of the cycle elimination algorithm has been verified by both simulation and hardware measurements, which show that the error floor is suppressed to a much lower level without incurring any performance penalty. The implemented decoder is tested in an experimental LDPC orthogonal frequency division multiplexing system and achieves the superior measured performance of block error rate below 10/sup -7/ at signal-to-noise ratio of 1.8 dB.
of the Dissertation Quantization of a Low-Density Parity-Check (LDPC) Decoder: Limited-Precision Digital Design of the Sum-Product Algorithm (SPA) for Wireless Voice and Video Communication Channels. by Raymond B Moberly Claremont Graduate University and San Diego State University: 2012 This dissertation presents two-bit and three-bit quantizations for Sum Product Algorithm (SPA) decoding of Low-Density Parity-Check (LDPC) codes. The study involves evaluation of both decoding performance and hardware implementation requirements. Trade-o s between these factors are considered. The quantizations are simulated in software to measure decoding performance. While quantization e ects are the focal point of the research, a comparison of the number of decoding iterations and of the number of bits of precision used in the decoder are both presented along with the quantization experiments. Decoder performance, measured in terms of both Bit Error Rate (BER) and Frame Error Rate (FER), is tested for each two-bit and three-bit quantization over a range of Signal to Noise Ratio (SNR) values. No single quantization outperforms all other quantizations for the entire tested SNR range. Analysis of the SPA is performed, revealing strategies for computational e ciency and digital design. The hardware designs combine the parity-check and variable-node update steps of the SPA into a single update computation. The update computation is implemented in a hardware design language (HDL), synthesized to programmable logic, and then tested on a Field Programmable Gate Array (FPGA). Hardware implementation requirements, as measured from the synthesis results, are evaluated and compared to a selection of other published works, particularly the work of Planjery et al. A exible implementation is proposed that can adapt the quantization as the channel conditions change.