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QUANTUM REALIZATION OF TERNARY ADDER CIRCUITS

Mozammel H. A. Khan

Ternary quantum circuits have recently been introduced to realize ternary logic functions. In this paper realizations of ternary half- and full-adder circuits using generalized ternary gates (GTG) are proposed, which are more efficient than the previously published realizations.

Jan 1, 200413 citations

Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits

Majid Haghparast, Asma Taheri Monfared

International Journal of Theoretical PhysicsFeb 21, 201712 citations

RSFQ multiplexer and demultiplexer

L Zheng, Nobuyuki Yoshikawa, Jiaqi Deng +3 more

An 1:8 RSFQ demultiplexer (DEMUX) and an 8:1 RSFQ multiplexer (MUX) were designed, simulated and optimized to operate at about 20 GHz. Both the inputs and outputs of the DEMUX are complementary dual-rail signals. The basic 2-bit DEMUX module is a self-clocked dual-rail T flip-flop. This DEMUX has a simpler structure than an earlier version of a data-driven-self-timed (DDST) DEMUX developed in our laboratory; however its simulated dc bias margin is (-20%, +20%), which is lower than the more complex device (-29%, +29%). The MUX takes lower data rate single-rail inputs and combines them sequentially into a single output. The complementary output is recovered from the output itself to facilitate interfacing to other dual-rail circuits on chip. The calculated dc bias margin is (-30 %, +28%). Circuit functionality is verified for the 2-bit MUX and the 2-bit DEMUX at low speed. An on-chip high-speed test system is designed to evaluate operation of the MUX and DEMUX at 20 GHz. The circuits are fabricated using a 1 kA/cm/sup 2/ niobium process at both UCB and HYPRES.An 1:8 RSFQ demultiplexer (DEMUX) and an 8:1 RSFQ multiplexer (MUX) were designed, simulated and optimized to operate at about 20 GHz. Both the inputs and outputs of the DEMUX are complementary dual-rail signals. The basic 2-bit DEMUX module is a self-clocked dual-rail T flip-flop. This DEMUX has a simpler structure than an earlier version of a data-driven-self-timed (DDST) DEMUX developed in our laboratory; however its simulated dc bias margin is (-20%, +20%), which is lower than the more complex device (-29%, +29%). The MUX takes lower data rate single-rail inputs and combines them sequentially into a single output. The complementary output is recovered from the output itself to facilitate interfacing to other dual-rail circuits on chip. The calculated dc bias margin is (-30 %, +28%). Circuit functionality is verified for the 2-bit MUX and the 2-bit DEMUX at low speed. An on-chip high-speed test system is designed to evaluate operation of the MUX and DEMUX at 20 GHz. The circuits are fabricated using a 1 kA/cm/sup 2/ niobium process at both UCB and HYPRES.

IEEE Transactions on Applied SuperconductivityJun 1, 199918 citations

Novel Realization of Some Ternary Circuits for Quantum Computing

Asif I. Khan, N. Nusrat, S.M. Khan +1 more

We present novel realization of ternary Toffoli gate and modified Fredkin gate for quantum computing using generalized ternary gate (GTG) which are truly realizable quantum gates. Our realization of ternary Toffoli gate is more efficient than the previous results and we are the first to realize the modified Fredkin gate using GTGs

IEEE Region 10 Conference (TENCON)Nov 1, 20061 citation

A Synthesis Method for Quaternary Quantum Logic Circuits

Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay

arXiv:1210.8055Lecture notes in computer scienceJan 1, 201214 citations

Design and Implementation of Multi-Qubit 3D Quantum Integrated Circuits

Andrew J. Bestwick, Alexander T. Papageorge, Matt Reagor +1 more

Bulletin of the American Physical SocietyMar 14, 20170 citations

Novel Realization of Quantum Ternary Mux and Demux

Abstract

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Novel Realization of Quantum Ternary Mux and Demux

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