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IEEE Region 10 Conference (TENCON)

Novel Realization of Some Ternary Circuits for Quantum Computing

Asif I. Khan, N. Nusrat, S.M. Khan, Mahmudul Hasan

Published Nov 1, 2006• 1 citation
Publisher

Abstract

We present novel realization of ternary Toffoli gate and modified Fredkin gate for quantum computing using generalized ternary gate (GTG) which are truly realizable quantum gates. Our realization of ternary Toffoli gate is more efficient than the previous results and we are the first to realize the modified Fredkin gate using GTGs
DOI
10.1109/tencon.2006.343816

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We present realization of ternary Toffoli gate and modified Fredkin gate for quantum computing on top of ion trap realizable Muthukrishnan-Stroud primitive gates. Our design methodology is based on first realizing the quantum circuits using generalized ternary gates and Feynman gates and then replacing them with their equivalent realization using Muthukrishnan-Stroud gates. Our realization of ternary Toffoli gate is more efficient than the previously published result and modified Fredkin gate is realized for the first time in literature using Muthukrishnan-Stroud gates.
Ternary quantum circuits play a significant role in future quantum computing technology because they have many advantages over binary quantum circuits. Subtraction is considered as being one of the key arithmetic operations; hence, subtractors are very essential for the construction of various computational units of quantum computers and other complex computational systems. In this paper, we have proposed the realization of a quantum reversible ternary half-subtractor circuit using a generalized ternary gate, a ternary Toffoli gate, and a ternary C2NOT gate. Based on the realization of the ternary half-subtractor, we proposed the realization of a ternary full-subtractor.
The designs using ternary logic exploit its logarithmic reduction in the number of qudits compared with the binary circuits. In this paper, we propose quantum ternary multiplication gate. We term it as QTMG. Then we present the symbol and the realization of QTMG. Researchers will be able to use this gate as well as its symbol and realizations in their future studies. We also present a new realization of ternary Toffoli gate in specific state. Moreover, in this paper, we propose 1-qutrit multiplier circuit. The symbol and the realization of the proposed 1-qutrit multiplier circuit are also provided. Afterward, we proposed ternary partial products generation circuit (TPPG) and summation network circuit in order to design quantum ternary 2-qutrit multiplier circuit. Overall, the proposed design of QTMG in this paper is suggested for the first time. In addition, the proposed realization of ternary Toffoli gate, TPPG, summation network and 2-qutrit multiplier circuits are compared with the existing designs and the improvements are reported. The proposed gate and circuits are realized using macro-level ternary gates which are built on the top of the ion-trap realizable 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.