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CD-ROM-Ausg.:#R#<br/>Information technology and electrical engineering - devices and systems, materials and technologies for the future : 51. IWK, Internationales Wissenschaftliches Kolloquium ; proceedings ; 11 - 15 September 2006 / Faculty of Electrical and Information Technology, Technische Universität Ilmenau. - Ilmenau : Verl. ISLE, 2006. - ISBN 3-938843-16-0

Development of RSFQ circular memories for arbitrary AC waveform synthesisers

E. Tolkacheva, M. Khabipov, Daniel Hagedorn, Friedrich-Im. Buchholz, J. Kohlmann, Jürgen Niemeyer

Published Jun 26, 2009• 0 citations

Abstract

We present the designs of circular Rapid Single Flux Quantum (RSFQ) shift registers which are to be used as local memories in an arbitrary AC waveform synthesiser for metrology applications and are based on the results of different optimisation approaches.It was possible to apply two different optimisation approaches to the circuits for comparison of the outcome.The first approach is based on fast logic simulations and results in 22 Josephson junctions per double-bit register stage, operating at a maximum clock frequency of 12 GHz at the value of 0.75 of the optimum global bias, and at 17 GHz and 21 GHz at the bias points 1.0 and 1.25, respectively.The second optimisation approach is based on solving the corresponding integro-differential equations and results in 11 junctions per double-bit stage at a maximum clock frequency of 17.6 GHz for the same value of the Stewart-McCumber parameter with bias current margins of ±30%, which should be compared with the maximum operating frequency at the bias point of 0.75 of the logic simulation approach.

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Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>

IEEE Transactions on Applied Superconductivity•Mar 1, 1993•8 citations

We present the designs of circular Rapid Single Flux Quantum (RSFQ) shift registers which are to be used as local memories in an arbitrary AC waveform synthesiser for metrology applications and are based on the results of different optimisation approaches.It was possible to apply two different optimisation approaches to the circuits for comparison of the outcome.The first approach is based on fast logic simulations and results in 22 Josephson junctions per double-bit register stage, operating at a maximum clock frequency of 12 GHz at the value of 0.75 of the optimum global bias, and at 17 GHz and 21 GHz at the bias points 1.0 and 1.25, respectively.The second optimisation approach is based on solving the corresponding integro-differential equations and results in 11 junctions per double-bit stage at a maximum clock frequency of 17.6 GHz for the same value of the Stewart-McCumber parameter with bias current margins of ±30%, which should be compared with the maximum operating frequency at the bias point of 0.75 of the logic simulation approach.

The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed im- plementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, laten- cies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency. I. INTRODUCTION Digital signal processors with multi-gigahertz clock rates and high bandwidth mixed-signal circuits (l) require fzst aid robust memory unit to store repeatedly used &ita. In Rapid single flux quantum (RSFQ) logic, serial memory imple- meuted with circular shift registers (CSR) is an ideal choice for this task. These registers can be used to store the coeffi- cients of a digital filter (2), the samples of an arbitraiy wave- foiin generator, etc. Circular shift registers are also used as tlie core element of computational units to perfoi-m residue nurn- ber system arithmetic (3). RSFQ circular shift registers com- bine short access time with high throughput and cai be easily interfaced to low-frequency, extei-nal semiconductor electrou- ics.

Shift registers operated in digital feedback mode and utilized as pseudo random noise generators are very attractive for application as noise standards in rf noise power metrology. The paper reports on the concept of the integrated circuits required, based on superconducting Rapid-Single-Flux-Quantum (RSFQ) logic, and realized in Nb/Al/sub 2/O/sub 3/-Al/Nb technology. The design and layout of an 8-bit shift register is presented. Measurement results are reported which prove correct functionality for clock frequencies up to 45 GHz for standard operation. Typical bias current margins for operation of the shift register are /spl plusmn/27%. Further narrow-band limited ranges of operation have been found up to 60 GHz.

The author presents the design and test results for a novel, buffered RSFQ shift register. The register design makes it possible to build a circular 64-b shift register which is insensitive to the clock pulse direction within the experimentally measured DC bias margin of +or-15%. The implementation of a large variety of unidirectional shift registers using either a buffered or a two-Josephson-junction cell design confirms an expected wide DC bias margin of +or-30% (for a 32-b) and high speed, up to 60 GHz (for a 4-b register). Among these circuits is a 256-b shift register. To the author's knowledge, this is the largest RSFQ circuit (533 junctions) reported to date. This shift register was tested to have a DC bias margin of +or-6% and proper high-speed operation up to 12 GHz.>

Rapid Single-Flux-Quantum Circuits Fabricated Using

\hbox{20}\hbox{-}\hbox{kA}/\hbox{cm}^{2}

\hbox{Nb}/\hbox{AlO}_{x}/\hbox{Nb}

Process

We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm2process based on conventional Nb/AlOx/Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.

The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system arithmetic. It is surprising that the successful recurrent operation of such a shift register has never been reported m the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits-the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These designs differ in the topology of the clock distribution network as well as the type of storage element employed in the data path. Two designs show satisfactory parameter margins and large maximum clock frequency.

Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>