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IEEE Transactions on Instrumentation and Measurement

Development of a rapid-single-flux-quantum shift register for applications in RF noise power metrology

W. Kessel, F.-I. Buchholz, M. Khabipov, R. Dolata, J. Niemeyer

Published Apr 1, 1997• 7 citations
Publisher

Abstract

Shift registers operated in digital feedback mode and utilized as pseudo random noise generators are very attractive for application as noise standards in rf noise power metrology. The paper reports on the concept of the integrated circuits required, based on superconducting Rapid-Single-Flux-Quantum (RSFQ) logic, and realized in Nb/Al/sub 2/O/sub 3/-Al/Nb technology. The design and layout of an 8-bit shift register is presented. Measurement results are reported which prove correct functionality for clock frequencies up to 45 GHz for standard operation. Typical bias current margins for operation of the shift register are /spl plusmn/27%. Further narrow-band limited ranges of operation have been found up to 60 GHz.

DOI
10.1109/19.571890

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IEEE Transactions on Applied Superconductivity•Mar 1, 1993•8 citations
Shift registers operated in digital feedback mode and utilized as pseudo random noise generators are very attractive for application as noise standards in rf noise power metrology. The paper reports on the concept of the integrated circuits required, based on superconducting Rapid-Single-Flux-Quantum (RSFQ) logic, and realized in Nb/Al/sub 2/O/sub 3/-Al/Nb technology. The design and layout of an 8-bit shift register is presented. Measurement results are reported which prove correct functionality for clock frequencies up to 45 GHz for standard operation. Typical bias current margins for operation of the shift register are /spl plusmn/27%. Further narrow-band limited ranges of operation have been found up to 60 GHz.
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of +or-23% and +or-14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO/sub x//Nb process with a junction critical current density of 1.0 kA/cm/sup 2/.>
Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.
The paper presents the determination of the high-frequency performance of Rapid Single Flux Quantum (RSFQ) circuits fabricated in superconductor-insulator-normal metal-insulator-superconductor (SINIS) technology. Circuits of different designs have been realized and were experimentally investigated, including specially designed T flip-flop (TFF) structures and circuits consisting of a switch terminated in Josephson transmission lines. For TFF circuits, the operational functionality was investigated in the frequency range from dc up to nearly 200 GHz. Two frequency domains were found. In the first domain, ranging up to frequencies of 80 GHz (f/sub C//spl cong/Y/sub C///spl Phi//sub 0/), correct digital operation of the device was ascertained. Beyond this range a second domain was found, ranging to nearly 200 GHz, for which quasi-analog frequency dividing is assumed. The bias current margins are /spl plusmn/30% at 40 GHz and /spl plusmn/15% between 130 GHz and 200 GHz. For circuits consisting of a switch, the operational functionality was proved in the frequency range from dc up to 50 GHz, with bias current margins of more than /spl plusmn/20%. The critical current density of the circuits is j/sub C//spl cong/750 A/cm/sup 2/. The smallest junction area is about A=12 /spl mu/m/sup 2/, and the characteristic voltage is V/sub C/=170 /spl mu/V.
Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>