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Design and Testing of Rapid Single Flux Quantum Shift Registers with Magnetically Coupled

Readout Gates, Perng-Fei Yuh, Oleg A. Mukhanov

Published Jan 1, 1992• 0 citations
OpenAlex

Abstract

Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.

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Superconductor Science and Technology•Mar 16, 2006•6 citations
Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of +or-23% and +or-14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO/sub x//Nb process with a junction critical current density of 1.0 kA/cm/sup 2/.>
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
We have designed and experimentally verified a test bench for high frequency testing of Rapid Single Flux Quantum (RSFQ) circuits. This test bench uses an external tuneable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift-register. The clock pattern is consequently shifted out at high speed and splitted to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed readout electronics. The test bench consists of 158 Josephson junctions and occupied area is 3300 * 660 (mikro meter)^2. It was\nexperimentally verified up to 33 GHz with +- 21.7 % margins on the global bias supply current.