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Superconductor Science and Technology

A high frequency test bench for rapid single-flux-quantum circuits

Henrik Engseth, Samuel Intiso, M R Rafique, E. Tolkacheva, Anna Kidiyarova-Shevchenko

Published Mar 16, 2006• 6 citations
Publisher

Abstract

We have designed and experimentally verified a test bench for high frequency testing of Rapid Single Flux Quantum (RSFQ) circuits. This test bench uses an external tuneable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift-register. The clock pattern is consequently shifted out at high speed and splitted to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed readout electronics. The test bench consists of 158 Josephson junctions and occupied area is 3300 * 660 (mikro meter)^2. It was\nexperimentally verified up to 33 GHz with +- 21.7 % margins on the global bias supply current.

DOI
10.1088/0953-2048/19/5/s44

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We have designed and experimentally verified a test bench for high frequency testing of Rapid Single Flux Quantum (RSFQ) circuits. This test bench uses an external tuneable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift-register. The clock pattern is consequently shifted out at high speed and splitted to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed readout electronics. The test bench consists of 158 Josephson junctions and occupied area is 3300 * 660 (mikro meter)^2. It was\nexperimentally verified up to 33 GHz with +- 21.7 % margins on the global bias supply current.
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.
Error rates of rapid-single-flux-quantum (RSFQ) shift register memories were investigated using a high-speed error-rate measurement system in order to demonstrate their reliability and stability. We designed and implemented an 8 times 8-bit shift register memory using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The total number of Josephson junctions including the test system is 4184, and the circuit area is 2.1 mm times 3.2 mm. We measured the error rates of every storage node by reading out the data 216times at the clock frequency of 16 GHz. The measured error rates were lower than 10-10with DC bias margin better than plusmn5%.
Testing on a single-flux-quantum (SFQ) shift register fabricated with a SFQ Nb-AlO/sub x/Nb Josephson junction process indicates that a stable flux quantum can be stored in a rapid SFQ (RSFQ) shift register stage and be shifted by SFQ pulses. Design simulations showed that logic errors can occur in SFQ shift registers even though the circuit passes the average voltage test. Three-junction-per-stage shift registers had an advantage over the two-junction-per-stage shift register in handling data with successive 1's and in incorporating resistors to increase tolerance of trapped magnetic flux. Input and output buffers for data and clock pulses were added to get an RSFQ shift register to obtain correct performance. The highest error-free operation speed for the data with successive 1's is about half of the speed for propagation of a lone data 1. Error-free operation of SFQ shift registers with three junctions per stage could be obtained up to speeds of 30-60 GHz with Josephson junctions having I/sub c/R/sub n/ (critical-current-normal-resistance product) values of 600 mu V.>
We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>