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Circular Shift Registers

C.A. Mancini, Nada Vukovic, Andrea M. Herr, Kris Gaj, Mark F. Bocko, M. J. Feldman

Published Jan 1, 1997• 0 citations
OpenAlex

Abstract

The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed im- plementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, laten- cies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency. I. INTRODUCTION Digital signal processors with multi-gigahertz clock rates and high bandwidth mixed-signal circuits (l) require fzst aid robust memory unit to store repeatedly used &ita. In Rapid single flux quantum (RSFQ) logic, serial memory imple- meuted with circular shift registers (CSR) is an ideal choice for this task. These registers can be used to store the coeffi- cients of a digital filter (2), the samples of an arbitraiy wave- foiin generator, etc. Circular shift registers are also used as tlie core element of computational units to perfoi-m residue nurn- ber system arithmetic (3). RSFQ circular shift registers com- bine short access time with high throughput and cai be easily interfaced to low-frequency, extei-nal semiconductor electrou- ics.

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The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system arithmetic. It is surprising that the successful recurrent operation of such a shift register has never been reported m the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits-the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These designs differ in the topology of the clock distribution network as well as the type of storage element employed in the data path. Two designs show satisfactory parameter margins and large maximum clock frequency.

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The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed im- plementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, laten- cies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency. I. INTRODUCTION Digital signal processors with multi-gigahertz clock rates and high bandwidth mixed-signal circuits (l) require fzst aid robust memory unit to store repeatedly used &ita. In Rapid single flux quantum (RSFQ) logic, serial memory imple- meuted with circular shift registers (CSR) is an ideal choice for this task. These registers can be used to store the coeffi- cients of a digital filter (2), the samples of an arbitraiy wave- foiin generator, etc. Circular shift registers are also used as tlie core element of computational units to perfoi-m residue nurn- ber system arithmetic (3). RSFQ circular shift registers com- bine short access time with high throughput and cai be easily interfaced to low-frequency, extei-nal semiconductor electrou- ics.
The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system arithmetic. It is surprising that the successful recurrent operation of such a shift register has never been reported m the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits-the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These designs differ in the topology of the clock distribution network as well as the type of storage element employed in the data path. Two designs show satisfactory parameter margins and large maximum clock frequency.
Circular shift registers (CSRs) can be used in the implementation of superconducting digital signal processing blocks requiring the storage of data that needs to be accessed periodically with short access times and high throughput rate. The clock distribution networks of these shift registers has the unique constraint that the overall clock skew must be zero. Centered around this requirement, a design methodology for the design of these circuits has previously been developed and presented, resulting in three different designs for 64-bit versions of CSRs. We now present experimental results of the functional testing of two of these designs. These results show correct operation up to 13 GHz and set an important step for the complete validation of the design methodology presented earlier.
A 64-bit superconducting rapid single flux quantum (RSFQ) circular shift register (CSR) has been demonstrated to operate at clock frequencies up to 18 GHz. The CSR was designed with special attention to timing constraints, which are more severe for "recurrent" circuits (where data must circulate around closed feedback loops) than for systolic arrays where only local timing constraints are relevant. The longest recurrent data path ever demonstrated previously was only several stages long. The testing scheme demonstrated here is unique in that the data circulated up to 50 million times before verification.
We present the designs of circular Rapid Single Flux Quantum (RSFQ) shift registers which are to be used as local memories in an arbitrary AC waveform synthesiser for metrology applications and are based on the results of different optimisation approaches.It was possible to apply two different optimisation approaches to the circuits for comparison of the outcome.The first approach is based on fast logic simulations and results in 22 Josephson junctions per double-bit register stage, operating at a maximum clock frequency of 12 GHz at the value of 0.75 of the optimum global bias, and at 17 GHz and 21 GHz at the bias points 1.0 and 1.25, respectively.The second optimisation approach is based on solving the corresponding integro-differential equations and results in 11 junctions per double-bit stage at a maximum clock frequency of 17.6 GHz for the same value of the Stewart-McCumber parameter with bias current margins of ±30%, which should be compared with the maximum operating frequency at the bias point of 0.75 of the logic simulation approach.
Abstract In this paper, a shift register (SR) memory based on rapid single flux quantum (RSFQ) logic for bit-parallel access is proposed. The memory cell changes from a row in the memory array to a column to increase the bit of data accessed per one clock cycle. The design of the 8 bit × 2 bit (8 × 2) memory is introduced. The memory consists of four parts: a SR memory array, an input buffer, an output buffer, and a controller, in which the controller is used to produce a control signal at a certain clock cycle specified by the address data. We have obtained the low speed test of the 8 × 2 memory fabricated by 6 kA cm −2 Nb process (SIMIT-Nb03), all bit-parallel access operations (write, read, clear and write, and read again) have been verified. We also simulated the 8 × 8 memory with data width expansion and obtained the maximum operating frequency of 34 GHz after the place and route with the SIMIT-Nb03 cell library. Based on the hierarchical storage, we have used the 8 × 8 memory as a basic block to construct large size of memory system, the access time and bandwidth have been evaluated. The bit-parallel memory shows higher bandwidth than bit-serial memory with the same capacity, especially for large capacity memory.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.