Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

RSFQ circular shift registers

C.A. Mancini, Nada Vukovic, Andrea M. Herr, Kris Gaj, Mark F. Bocko, M. J. Feldman

Published Jun 1, 1997• 26 citations
Publisher

Abstract

The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system arithmetic. It is surprising that the successful recurrent operation of such a shift register has never been reported m the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits-the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These designs differ in the topology of the clock distribution network as well as the type of storage element employed in the data path. Two designs show satisfactory parameter margins and large maximum clock frequency.

DOI
10.1109/77.621826

Related papers

Circular Shift Registers

C.A. Mancini, Nada Vukovic, Andrea M. Herr +3 more

The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed im- plementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, laten- cies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency. I. INTRODUCTION Digital signal processors with multi-gigahertz clock rates and high bandwidth mixed-signal circuits (l) require fzst aid robust memory unit to store repeatedly used &ita. In Rapid single flux quantum (RSFQ) logic, serial memory imple- meuted with circular shift registers (CSR) is an ideal choice for this task. These registers can be used to store the coeffi- cients of a digital filter (2), the samples of an arbitraiy wave- foiin generator, etc. Circular shift registers are also used as tlie core element of computational units to perfoi-m residue nurn- ber system arithmetic (3). RSFQ circular shift registers com- bine short access time with high throughput and cai be easily interfaced to low-frequency, extei-nal semiconductor electrou- ics.

•Jan 1, 1997•0 citations

Experimental investigation of RSFQ circular shift registers

Cesar A. Mancini, Nada Vukovic, Mark F. Bocko +2 more

Circular shift registers (CSRs) can be used in the implementation of superconducting digital signal processing blocks requiring the storage of data that needs to be accessed periodically with short access times and high throughput rate. The clock distribution networks of these shift registers has the unique constraint that the overall clock skew must be zero. Centered around this requirement, a design methodology for the design of these circuits has previously been developed and presented, resulting in three different designs for 64-bit versions of CSRs. We now present experimental results of the functional testing of two of these designs. These results show correct operation up to 13 GHz and set an important step for the complete validation of the design methodology presented earlier.

Applied Superconductivity•Oct 1, 1999•1 citation

High-speed operation of a 64-bit circular shift register

Andrea M. Herr, C.A. Mancini, Nada Vukovic +2 more

A 64-bit superconducting rapid single flux quantum (RSFQ) circular shift register (CSR) has been demonstrated to operate at clock frequencies up to 18 GHz. The CSR was designed with special attention to timing constraints, which are more severe for "recurrent" circuits (where data must circulate around closed feedback loops) than for systolic arrays where only local timing constraints are relevant. The longest recurrent data path ever demonstrated previously was only several stages long. The testing scheme demonstrated here is unique in that the data circulated up to 50 million times before verification.

IEEE Transactions on Applied Superconductivity•Jan 1, 1998•15 citations

Development of RSFQ circular memories for arbitrary AC waveform synthesisers

E. Tolkacheva, M. Khabipov, Daniel Hagedorn +3 more

We present the designs of circular Rapid Single Flux Quantum (RSFQ) shift registers which are to be used as local memories in an arbitrary AC waveform synthesiser for metrology applications and are based on the results of different optimisation approaches.It was possible to apply two different optimisation approaches to the circuits for comparison of the outcome.The first approach is based on fast logic simulations and results in 22 Josephson junctions per double-bit register stage, operating at a maximum clock frequency of 12 GHz at the value of 0.75 of the optimum global bias, and at 17 GHz and 21 GHz at the bias points 1.0 and 1.25, respectively.The second optimisation approach is based on solving the corresponding integro-differential equations and results in 11 junctions per double-bit stage at a maximum clock frequency of 17.6 GHz for the same value of the Stewart-McCumber parameter with bias current margins of ±30%, which should be compared with the maximum operating frequency at the bias point of 0.75 of the logic simulation approach.

CD-ROM-Ausg.:#R#<br/>Information technology and electrical engineering - devices and systems, materials and technologies for the future : 51. IWK, Internationales Wissenschaftliches Kolloquium ; proceedings ; 11 - 15 September 2006 / Faculty of Electrical and Information Technology, Technische Universität Ilmenau. - Ilmenau : Verl. ISLE, 2006. - ISBN 3-938843-16-0•Jun 26, 2009•0 citations

Design and component test of SFQ shift register memories

K. Fujiwara, H. Hoshina, Y. Yamashiro +1 more

The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•14 citations

Rapid single flux quantum (RSFQ) shift register family

Oleg A. Mukhanov

The author presents the design and test results for a novel, buffered RSFQ shift register. The register design makes it possible to build a circular 64-b shift register which is insensitive to the clock pulse direction within the experimentally measured DC bias margin of +or-15%. The implementation of a large variety of unidirectional shift registers using either a buffered or a two-Josephson-junction cell design confirms an expected wide DC bias margin of +or-30% (for a 32-b) and high speed, up to 60 GHz (for a 4-b register). Among these circuits is a 256-b shift register. To the author's knowledge, this is the largest RSFQ circuit (533 junctions) reported to date. This shift register was tested to have a DC bias margin of +or-6% and proper high-speed operation up to 12 GHz.>

IEEE Transactions on Applied Superconductivity•Mar 1, 1993•79 citations
The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system arithmetic. It is surprising that the successful recurrent operation of such a shift register has never been reported m the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits-the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These designs differ in the topology of the clock distribution network as well as the type of storage element employed in the data path. Two designs show satisfactory parameter margins and large maximum clock frequency.
The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed im- plementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, laten- cies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency. I. INTRODUCTION Digital signal processors with multi-gigahertz clock rates and high bandwidth mixed-signal circuits (l) require fzst aid robust memory unit to store repeatedly used &ita. In Rapid single flux quantum (RSFQ) logic, serial memory imple- meuted with circular shift registers (CSR) is an ideal choice for this task. These registers can be used to store the coeffi- cients of a digital filter (2), the samples of an arbitraiy wave- foiin generator, etc. Circular shift registers are also used as tlie core element of computational units to perfoi-m residue nurn- ber system arithmetic (3). RSFQ circular shift registers com- bine short access time with high throughput and cai be easily interfaced to low-frequency, extei-nal semiconductor electrou- ics.
Circular shift registers (CSRs) can be used in the implementation of superconducting digital signal processing blocks requiring the storage of data that needs to be accessed periodically with short access times and high throughput rate. The clock distribution networks of these shift registers has the unique constraint that the overall clock skew must be zero. Centered around this requirement, a design methodology for the design of these circuits has previously been developed and presented, resulting in three different designs for 64-bit versions of CSRs. We now present experimental results of the functional testing of two of these designs. These results show correct operation up to 13 GHz and set an important step for the complete validation of the design methodology presented earlier.
A 64-bit superconducting rapid single flux quantum (RSFQ) circular shift register (CSR) has been demonstrated to operate at clock frequencies up to 18 GHz. The CSR was designed with special attention to timing constraints, which are more severe for "recurrent" circuits (where data must circulate around closed feedback loops) than for systolic arrays where only local timing constraints are relevant. The longest recurrent data path ever demonstrated previously was only several stages long. The testing scheme demonstrated here is unique in that the data circulated up to 50 million times before verification.
We present the designs of circular Rapid Single Flux Quantum (RSFQ) shift registers which are to be used as local memories in an arbitrary AC waveform synthesiser for metrology applications and are based on the results of different optimisation approaches.It was possible to apply two different optimisation approaches to the circuits for comparison of the outcome.The first approach is based on fast logic simulations and results in 22 Josephson junctions per double-bit register stage, operating at a maximum clock frequency of 12 GHz at the value of 0.75 of the optimum global bias, and at 17 GHz and 21 GHz at the bias points 1.0 and 1.25, respectively.The second optimisation approach is based on solving the corresponding integro-differential equations and results in 11 junctions per double-bit stage at a maximum clock frequency of 17.6 GHz for the same value of the Stewart-McCumber parameter with bias current margins of ±30%, which should be compared with the maximum operating frequency at the bias point of 0.75 of the logic simulation approach.
The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.
The author presents the design and test results for a novel, buffered RSFQ shift register. The register design makes it possible to build a circular 64-b shift register which is insensitive to the clock pulse direction within the experimentally measured DC bias margin of +or-15%. The implementation of a large variety of unidirectional shift registers using either a buffered or a two-Josephson-junction cell design confirms an expected wide DC bias margin of +or-30% (for a 32-b) and high speed, up to 60 GHz (for a 4-b register). Among these circuits is a 256-b shift register. To the author's knowledge, this is the largest RSFQ circuit (533 junctions) reported to date. This shift register was tested to have a DC bias margin of +or-6% and proper high-speed operation up to 12 GHz.>