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Applied Superconductivity

Experimental investigation of RSFQ circular shift registers

Cesar A. Mancini, Nada Vukovic, Mark F. Bocko, M. J. Feldman, Andrea M. Herr

Published Oct 1, 1999• 1 citation
Publisher

Abstract

Circular shift registers (CSRs) can be used in the implementation of superconducting digital signal processing blocks requiring the storage of data that needs to be accessed periodically with short access times and high throughput rate. The clock distribution networks of these shift registers has the unique constraint that the overall clock skew must be zero. Centered around this requirement, a design methodology for the design of these circuits has previously been developed and presented, resulting in three different designs for 64-bit versions of CSRs. We now present experimental results of the functional testing of two of these designs. These results show correct operation up to 13 GHz and set an important step for the complete validation of the design methodology presented earlier.

DOI
10.1016/s0964-1807(99)00046-0

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Circular shift registers (CSRs) can be used in the implementation of superconducting digital signal processing blocks requiring the storage of data that needs to be accessed periodically with short access times and high throughput rate. The clock distribution networks of these shift registers has the unique constraint that the overall clock skew must be zero. Centered around this requirement, a design methodology for the design of these circuits has previously been developed and presented, resulting in three different designs for 64-bit versions of CSRs. We now present experimental results of the functional testing of two of these designs. These results show correct operation up to 13 GHz and set an important step for the complete validation of the design methodology presented earlier.
The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed im- plementation of residue number system anthmetic. It is then sur rising that the successful recurrent operation of such a s&ft register has never been reported in the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits--the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, laten- cies and areas. These desi ns differ in the topology of the clock distribution networf as well as the ty e of storage element employed in the data path. Two fesigns show satisfactory parameter margins and large maximum clock frequency. I. INTRODUCTION Digital signal processors with multi-gigahertz clock rates and high bandwidth mixed-signal circuits (l) require fzst aid robust memory unit to store repeatedly used &ita. In Rapid single flux quantum (RSFQ) logic, serial memory imple- meuted with circular shift registers (CSR) is an ideal choice for this task. These registers can be used to store the coeffi- cients of a digital filter (2), the samples of an arbitraiy wave- foiin generator, etc. Circular shift registers are also used as tlie core element of computational units to perfoi-m residue nurn- ber system arithmetic (3). RSFQ circular shift registers com- bine short access time with high throughput and cai be easily interfaced to low-frequency, extei-nal semiconductor electrou- ics.
A 64-bit superconducting rapid single flux quantum (RSFQ) circular shift register (CSR) has been demonstrated to operate at clock frequencies up to 18 GHz. The CSR was designed with special attention to timing constraints, which are more severe for "recurrent" circuits (where data must circulate around closed feedback loops) than for systolic arrays where only local timing constraints are relevant. The longest recurrent data path ever demonstrated previously was only several stages long. The testing scheme demonstrated here is unique in that the data circulated up to 50 million times before verification.
The circular shift register is a versatile building block for RSFQ digital circuits. It can be used for local memory and it is essential for the proposed implementation of residue number system arithmetic. It is surprising that the successful recurrent operation of such a shift register has never been reported m the RSFQ literature. Circular shift registers have a design constraint that is unusual in RSFQ circuits-the requirement of zero overall clock skew. We propose and analyze three novel designs and compare their simulated parameter margins as well as their maximum operating frequencies, latencies and areas. These designs differ in the topology of the clock distribution network as well as the type of storage element employed in the data path. Two designs show satisfactory parameter margins and large maximum clock frequency.
The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.
This dissertation presents the design, fabrication, and testing of a flux-shuttle shift register and a discussion of computer architecture and systems for various superconducting digital logic families. While superconductive digital logic provides very fast switching speed (a few picoseconds), it is necessary to carefully consider the application and the computer architecture being used to implement a digital system when designing for maximum performance. The first part of this dissertation addresses architecture issues. First, a brief description of superconducting digital logic fundamentals is provided. The basic concepts of various techniques used in current high-performance computing systems are then presented. Since system architecture is greatly influenced by the characteristics of the logic family used, we then describe three superconducting logic types in detail. The characteristics of each of these logic families are examined, and their influence on architecture is discussed. The system requirements of general-purpose computing and digital signal processing are investigated. Due to the demands placed on random access memory by general-purpose computing, we conclude that the most practical digital system currently realizable in superconducting technology is based on digital signal processing (DSP). Finally, three example DSP systems are explored. Part II of this dissertation concentrates on the design, fabrication, and testing of a shift register, an important part of many DSP systems. Several shift registers using different logic types are evaluated. The design and testing of a flux-shuttle shift register using direct injection clocks are presented. The circuit was experimentally verified to work with wide operating margins at low speed. While simulations indicate that the shift register will operate at more than 60 GHz, high-speed test of the shift register was limited to 1 GHz by available test equipment.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.