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Journal of Circuits and Systems

Parallel encoding /decoding architecture for π-rotation LDPC codes

Feng Guang-zeng

Published Jan 1, 2011• 0 citations
OpenAlex

Abstract

We propose partial parallel encoding/decoding architectures for π-rotation LDPC codes based on the rotating structure of permutation matrices.Two-dimensional arrays are designed to store the iterative information;therefore the variable/check messages needed in iterations can be retrieved out by the mapping architectures.Those rotation architectures can also reduce the message transmission complexity,therefore increase the throughput of LDPC decoders.The decoding architectures are suitable for reprogrammable,and can achieve a good tradeoff between hardware complexity and decoding throughput.

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We propose partial parallel encoding/decoding architectures for π-rotation LDPC codes based on the rotating structure of permutation matrices.Two-dimensional arrays are designed to store the iterative information;therefore the variable/check messages needed in iterations can be retrieved out by the mapping architectures.Those rotation architectures can also reduce the message transmission complexity,therefore increase the throughput of LDPC decoders.The decoding architectures are suitable for reprogrammable,and can achieve a good tradeoff between hardware complexity and decoding throughput.
This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.
This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.
Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the design of a parallel-serial decoder architecture that can be used to map any LDPC code with such a structure to a hardware emulation platform. High-throughput emulation allows for the exploration of the low bit-error rate (BER) region and provides statistics of the error traces, which illuminate the causes of the error floors of the (2048, 1723) Reed-Solomon based LDPC (RS-LDPC) code and the (2209, 1978) array-based LDPC code. Two classes of error events are observed: oscillatory behavior and convergence to a class of non-codewords, termed absorbing sets. The influence of absorbing sets can be exacerbated by message quantization and decoder implementation. In particular, quantization and the log-tanh function approximation in sum-product decoders
Abstract—Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the design of a parallel-serial decoder architecture that can be used to map any LDPC code with such a structure to a hardware emulation platform. High-throughput emulation allows for the exploration of the low bit-error rate (BER) region and provides statistics of the error traces, which illuminate the causes of the error floors of the (2048, 1723) Reed-Solomon based LDPC (RS-LDPC) code and the (2209, 1978) array-based LDPC code. Two classes of error events are observed: oscillatory behavior and convergence to a class of non-codewords, termed absorbing sets. The influence of absorbing sets can be exacerbated by message quantization and decoder implementation. In particular, quantization and the log-tanh function approximation in sum-product decoders
Quasi-cyclic low density parity check (LDPC) codes and rotation LDPC codes are investigated in this paper, based on which, a new class of well-structured LDPC codes are proposed. Additionally, for ease of coding, a dual-diagonal structure is applied to the parity-check matrices of those codes, which ensure that parity-check bits can be recursively calculated with linear computational complexity. With the rotating and cyclic shift structure, decoders can be effectively implemented with partially parallel architecture appeared in some literatures on QC-LDPC codes and other structured LDPC codes. Simulation results show that the proposed structured LDPC codes are feasible.
In this article we present a fully programmable and scalable partly-parallel LDPC decoder architecture together with an optimum mapping and scheduling algorithm. The proposed algorithm exploits the full parallelism of the architecture at any time for any code, which means that the mapping algorithm achieves 100% utilization of the architecture. The proposed design is fully programmable and can be reconfigured for a different LDPC code by changing the initialization of the control memory. Thus the architecture can be used for a multi-standard decoder which supports decoding of any structured or unstructured LDPC code. Furthermore, the parallelism of the architecture is unconstrained and fully scalable which allows to exchange hardware cost and throughput with fine granularity. In contrast to previously proposed programmable designs our approach uses parallel variable and check node processing and thus doubles the data throughput.