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IEEE International Conference on Solid-State and Integrated Circuit Technology

Reduced complexity look-up table based π-rotation LDPC decoder

Hao Wang, Hongda Wang, Gerald E. Sobelman, Chiu‐Sing Choy

Published Oct 1, 2016• 0 citations
Publisher

Abstract

This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.

DOI
10.1109/icsict.2016.7998936

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This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.
Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of Eb/N0E_b/N_0Eb​/N0​ Eb/N0 until the BER of 1e−6.
Abstract Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.
This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.
In this work, a high performance LDPC decoder architecture is presented. It is a partially-parallel architecture for low-complexity consideration. In order to eliminate the idling time and hardware complexity in conventional partially-parallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the parity-check matrix is optimally partitioned into four unequal sub-matrices that lead to high efficiency in hardware sharing. As a result, it can handle two different codewords simultaneously with 100% hardware utilization. Furthermore, for minimizing the performance loss due to round-off errors in fixed-point implementations, the well-known modified min-sum decoding algorithm is enhanced by our recently proposed high-performance CMVP decoding algorithm. Overall, the proposed decoder has high throughput, low complexity, and good BER performances. In the circuit implementation example of the (576, 288) parity check matrix for IEEE 802.16e standard, the decoder achieves a data rate of 5.5Gbps assuming 10 decoding iterations and 7 quantization bits, with a small area of 653K gates, based on UMC 90nm process technology.
In this paper, we present a rate-compatible LDPC decoder architecture which supports code rates between the rate of the mother code and 1. The rate-1/2 2304-bit Quasi-Cyclic (QC) LDPC codes with dual-diagonal parity check structure is selected from WiMax standard as the mother code and is punctured using specific puncturing patterns to obtain arbitrary rates. Parallel layered decoding architecture (PLDA) is employed to reduce chip area and improve the throughput. Simulation results show that the proposed punctured codes have comparable error correcting performances with the performances of dedicated codes from WiMax standard. The decoder is implemented on the platform of Xilinx XC2V8000. Compared with previous WiMax LDPC decoders synthesized by the same device, our low-complexity decoder consumes less FPGA resources: reduction of slices by 63%, flip-flops by 73%, look-up tables (LUTs) by 60% and RAMs by 30%.