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Asilomar Conference on Signals, Systems and Computers (ACSSC)

A low-complexity rate-compatible LDPC decoder

Kai Zhang, Xinming Huang

Published Jan 1, 2009• 6 citations
Publisher

Abstract

In this paper, we present a rate-compatible LDPC decoder architecture which supports code rates between the rate of the mother code and 1. The rate-1/2 2304-bit Quasi-Cyclic (QC) LDPC codes with dual-diagonal parity check structure is selected from WiMax standard as the mother code and is punctured using specific puncturing patterns to obtain arbitrary rates. Parallel layered decoding architecture (PLDA) is employed to reduce chip area and improve the throughput. Simulation results show that the proposed punctured codes have comparable error correcting performances with the performances of dedicated codes from WiMax standard. The decoder is implemented on the platform of Xilinx XC2V8000. Compared with previous WiMax LDPC decoders synthesized by the same device, our low-complexity decoder consumes less FPGA resources: reduction of slices by 63%, flip-flops by 73%, look-up tables (LUTs) by 60% and RAMs by 30%.

DOI
10.1109/acssc.2009.5469954

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In this paper, we present a rate-compatible LDPC decoder architecture which supports code rates between the rate of the mother code and 1. The rate-1/2 2304-bit Quasi-Cyclic (QC) LDPC codes with dual-diagonal parity check structure is selected from WiMax standard as the mother code and is punctured using specific puncturing patterns to obtain arbitrary rates. Parallel layered decoding architecture (PLDA) is employed to reduce chip area and improve the throughput. Simulation results show that the proposed punctured codes have comparable error correcting performances with the performances of dedicated codes from WiMax standard. The decoder is implemented on the platform of Xilinx XC2V8000. Compared with previous WiMax LDPC decoders synthesized by the same device, our low-complexity decoder consumes less FPGA resources: reduction of slices by 63%, flip-flops by 73%, look-up tables (LUTs) by 60% and RAMs by 30%.
This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations
A multi-rate decoder of Quasi-Cyclic LDPC(QC-LDPC) decoder is presented based on the improvement of layered decoding algorithm.The implementation has larger bit throughput resulting from fast convergence speed by more than 50 percent in terms of decoding iterations.Only four memories are used to store the messages which significantly reduce the area and the power dissipation.Adjusted integer quantization of layered decoding algorithm for check-node updating reduces the complexity and the correction factor guarantees the error rate performance.The proposed decoding architecture is implemented in the standard recommended.The decoder consumes 0.6 million gates,and reaches a throughput of 134 Mb/s at a clock frequency of 110 MHz with rate of 1/2.
The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as simplified code representations in the encoder and decoder. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. The decoder uses check node merging to increase the convergence speed of the algorithm. Check node merging allows the decoder to achieve the same performance with a significantly lower number of iterations, thereby increasing the throughput. The feasibility of a check node merging decoder is investigated for codes from IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the check node merging algorithm allows the decoder to be implemented using lower parallelization factors, thereby reducing the logic complexity. The designs have been synthesized to an Altera Cyclone II FPGA, and results show significant increases in throughput at high SNR.
A class of rate-compatible (RC) quasi-cycle low-density parity-check (QC-LDPC) codes that have linear encodable complexity and low error floor is presented. To ensure linear encoding complexity, a lower triangular (LT) form for the parity part of the mother parity-check matrix is designed. By the designed LT form, a recursive encoding strategy is proposed. This encoding strategy can achieve linear encodable complexity, which is completely proportional to the code length. To guarantee good performances for a wide range of code rates, a layered short-cycle optimization algorithm is designed to obtain good girth distribution, and a layered density evolution algorithm is used to optimize degree distributions of each code rate. Then, a class of RC QC-LDPC codes can be obtained by both extension and puncturing from the optimized QC-LDPC mother code with rate 1/2. Simulation results show that no error floor is exhibited for the proposed RC QC-LDPC codes at FER=10-5. The practical performance at BER=10-6shows a gap of about 1.477 dB to the Shannon limit.
Nonbinary low-density parity-check (NB-LDPC) codes constructed over GF(q) (q >; 2) can achieve higher coding gain than binary LDPC codes when the code length is moderate. A complete partial-parallel decoder architecture based on the Min-max algorithm is proposed for quasi-cyclic NB-LDPC codes in this paper. A novel scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In our design, layered decoding is applied and only nm5) has also been synthesized on a Xilinx Virtex-2 Pro FPGA device. It can achieve a throughput of 9.30 Mbps when 15 decoding iterations are carried out.
The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as sharing of the encoder and decoder implementations between the codes of different rates. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. Assuming the use of a code ensemble obtained through puncturing of a low-rate mother code, the decoder achieves significantly reduced convergence rates by merging the check node neighbours of the punctured variable nodes. The architecture uses the minsum algorithm with serial node processing elements to efficiently handle the wide spread of node degrees that results from the merging of the check nodes.