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IET Communications

Parallel reconfigurable decoder architectures for rotation LDPC codes

Zijian Dong, G.-Z. Feng

Published Jan 12, 2010• 2 citations
Publisher

Abstract

This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.

DOI
10.1049/iet-com.2009.0209

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This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.
We propose partial parallel encoding/decoding architectures for π-rotation LDPC codes based on the rotating structure of permutation matrices.Two-dimensional arrays are designed to store the iterative information;therefore the variable/check messages needed in iterations can be retrieved out by the mapping architectures.Those rotation architectures can also reduce the message transmission complexity,therefore increase the throughput of LDPC decoders.The decoding architectures are suitable for reprogrammable,and can achieve a good tradeoff between hardware complexity and decoding throughput.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
Quasi-cyclic low density parity check (LDPC) codes and rotation LDPC codes are investigated in this paper, based on which, a new class of well-structured LDPC codes are proposed. Additionally, for ease of coding, a dual-diagonal structure is applied to the parity-check matrices of those codes, which ensure that parity-check bits can be recursively calculated with linear computational complexity. With the rotating and cyclic shift structure, decoders can be effectively implemented with partially parallel architecture appeared in some literatures on QC-LDPC codes and other structured LDPC codes. Simulation results show that the proposed structured LDPC codes are feasible.
In this paper, we propose a low-complexity entirely-overlapped partially-parallel decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. For a (c, t)-regular QC-LDPC decoder, this decoder can achieve approximate 100% hardware utilization efficiency (HUE) and entirely overlapped decoding by using only one check node process unit group (CNUG) to process c groups of check node messages sequentially. Compared with traditional partially-parallel decoder, the quantities of check node process unit (CNU), barrel shifters and counters can be decreased prominently. Moreover, it is flexible in code rate and code length.
π-rotation LDPC codes are characterized by their simple encoding structure,little memory requirement and easy circuit implementation.A new regular encoding structure for π-rotation LDPC codes is provided,whose parity check matrix His described by a few indexes and the number of which is less than the code length.This encoding structure is also easy to adjust code rate and code length.A new simple but efficient encoding scheme is also given to encode codeword with the aid of the indexes.Two-dimension arrays are used to store the belief information between check nodes and variable nodes,and then the BP Algorithm is developed.Simulation results indicate that these codes perform as well as regular low-density parity check codes based on completely random matrix constructions.
Quasi-cyclic (QC) low-density parity-check (LDPC) codes have advantages over other types of LDPC codes due to their cyclic shifting property. In this paper, a partially parallel QC-LDPC decoder with efficient memory design is proposed. To improve the memory utilization, the structures of efficient chunk and predictor are realized. The efficient chunk can store parts of check-to-variable messages. This design can effectively reduce the memory requirement. Furthermore, the predictor verifies variable-to-check messages and updates efficient chunks instantly. With less check-to-variable messages and variable-to-check messages stored in the memory, this decoding architecture only deposits few messages in several efficient chunks, such that the cost of memory is less. Eventually, the proposed approach dramatically reduces memory requirement about 65% compared to the traditional method while maintaining the same low-cost.