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International Conference on Advanced Computer Theory and Engineering

Design of structured LDPC codes with quasi-cyclic and rotation architecture

Qiao Guo-lei, Zijian Dong

Published Aug 1, 2010• 3 citations
Publisher

Abstract

Quasi-cyclic low density parity check (LDPC) codes and rotation LDPC codes are investigated in this paper, based on which, a new class of well-structured LDPC codes are proposed. Additionally, for ease of coding, a dual-diagonal structure is applied to the parity-check matrices of those codes, which ensure that parity-check bits can be recursively calculated with linear computational complexity. With the rotating and cyclic shift structure, decoders can be effectively implemented with partially parallel architecture appeared in some literatures on QC-LDPC codes and other structured LDPC codes. Simulation results show that the proposed structured LDPC codes are feasible.

DOI
10.1109/icacte.2010.5578934

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Quasi-cyclic low density parity check (LDPC) codes and rotation LDPC codes are investigated in this paper, based on which, a new class of well-structured LDPC codes are proposed. Additionally, for ease of coding, a dual-diagonal structure is applied to the parity-check matrices of those codes, which ensure that parity-check bits can be recursively calculated with linear computational complexity. With the rotating and cyclic shift structure, decoders can be effectively implemented with partially parallel architecture appeared in some literatures on QC-LDPC codes and other structured LDPC codes. Simulation results show that the proposed structured LDPC codes are feasible.
In this paper, a novel methodology for designing structured generalized low-density parity-check (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call low-density parity-check (LDPC) code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.
Based on the structure of parity-check matrix of RU algorithm,a class of Quasi-cycle Low-density Parity-check(QC-LDPC) codes with complexity is constructed by selecting sub-matrices reasonably to restrict and consisting of lower dual diagonal matrices.Simulation results show that not only the proposed codes have lower complexity,but also the error-correcting performance is better than QC-LDPC codes randomly constructed and practical Block-LDPC codes in the additive white Gaussion noise channel.It can get 0.3 dB Signal to Noise Ratio(SNR) gain at a Bit Error Rate(BRE) of 10-6.
There are many low-density parity-check (LDPC) decoder architectures in the literature most of which are based on structured codes. Besides been specific to a particular class of codes, suggested architectures are limited in scalability. The major challenge in decoder design and implementation is the consideration of several strongly interrelated factors. These factors affect decoder computation and communication complexity, and error-correcting performance. In this paper we present a low-complexity, flexible and scalable LDPC decoder architecture for quasi-cyclic codes that supports multiple code designs (size, weights, rates, regular and irregular). The architecture is a result of a combination of flexible code construction and computation overlapping techniques. The architecture is based on overlapping techniques that allow sequential processing of check and variable nodes. The overlapping techniques lead to a low-complexity decoder interconnect compared to the existing techniques as they allow serial processing of code sub-matrices as compared to parallel processing of all sub-matrices in the existing overlapping technique. Although the architecture is based on quasi-cyclic codes, it can also be applied to random or other structured codes making it the most flexible, scalable and high-throughput partly-parallel LDPC decoder architecture.
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.
This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.
In this paper, a novel methodology for designing structured generalized LDPC (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call LDPC code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.