Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

A flexible and overlapped QC-LDPC decoder

Gabofetswe Malema

Published Oct 1, 2008• 1 citation
Publisher

Abstract

There are many low-density parity-check (LDPC) decoder architectures in the literature most of which are based on structured codes. Besides been specific to a particular class of codes, suggested architectures are limited in scalability. The major challenge in decoder design and implementation is the consideration of several strongly interrelated factors. These factors affect decoder computation and communication complexity, and error-correcting performance. In this paper we present a low-complexity, flexible and scalable LDPC decoder architecture for quasi-cyclic codes that supports multiple code designs (size, weights, rates, regular and irregular). The architecture is a result of a combination of flexible code construction and computation overlapping techniques. The architecture is based on overlapping techniques that allow sequential processing of check and variable nodes. The overlapping techniques lead to a low-complexity decoder interconnect compared to the existing techniques as they allow serial processing of code sub-matrices as compared to parallel processing of all sub-matrices in the existing overlapping technique. Although the architecture is based on quasi-cyclic codes, it can also be applied to random or other structured codes making it the most flexible, scalable and high-throughput partly-parallel LDPC decoder architecture.

DOI
10.1109/icosp.2008.4697474

Related papers

Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes

Daesun Oh, Keshab K. Parhi

In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.

IEEE International Symposium on Circuits and Systems proceedings•May 1, 2007•14 citations

Low-complexity entirely-overlapped parallel decoder architecture for quasi-cyclic LDPC codes

Weizhi Lu, Piming Ma

In this paper, we propose a low-complexity entirely-overlapped partially-parallel decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. For a (c, t)-regular QC-LDPC decoder, this decoder can achieve approximate 100% hardware utilization efficiency (HUE) and entirely overlapped decoding by using only one check node process unit group (CNUG) to process c groups of check node messages sequentially. Compared with traditional partially-parallel decoder, the quantities of check node process unit (CNU), barrel shifters and counters can be decreased prominently. Moreover, it is flexible in code rate and code length.

International Conference on Advanced Communication Technology•Feb 15, 2009•0 citations

Flexible low-complexity decoding architecture for QC-LDPC codes

Nan Jiang, Kewu Peng, Zhixing Yang

A novel flexible decoding architecture for quasi-cyclic (QC) low-density parity-check (LDPC) code is proposed in this paper to reduce decoding complexity. The novelty of this architecture lies in a new time-sharing scheme of processing units, which provides low complexity and flexible serial factor of decoding hardware. Without loss of coding performance, the architecture requires significantly less processing units compared with known semi-parallel decoders at the expense of throughput decrease, while keeping memory requirement unchanged. As demonstrated by hardware and software implementation results, the proposed architecture is advisable and competent for wireless mobile systems and portable devices.

IEEE International Conference on Communication Systems (ICCS)•Nov 1, 2008•2 citations

A flexible layered LDPC decoder

Ioannis Tsatsaragkos, Vassilis Paliouras

We introduce a flexible layered decoder architecture for Quasi-Cyclic Low Density Parity Check (LDPC) codes. An iterative construction of the parity check matrix is exploited by the proposed decoder to achieve various degrees of parallelism, characterized by a high utilization of variable and check processing nodes, absence of memory conflicts, and a simple and scalable interconnection network. Furthermore, the proposed LDPC decoder supports variable code rate, information-word length and order of modulation. A comparison to prior-art decoders proves the efficiency of the proposed scheme.

International Symposium on Wireless Communication Systems•Nov 1, 2011•9 citations

A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz

Abstract—Hardware implementation of partially-parallel Low-Density Parity-Check (LDPC) decoders using unstructured random matrices is very complex and requires huge hardware resources. To alleviate the complexity and minimize resource requirements, structured LDPC matrices are used. This paper presents a novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) structured matrix for LDPC decoder. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMAX, WLAN and DVB-S2. In addition, different combinations of permuted sub-matrices are inserted in layers at different levels of matrix hierarchy to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated using the proposed technique have a marginal loss of less than 0.1 dB at a bit error rate (BER) performance 10-5 compared to unstructured random matrices. A hardware model of the proposed matrix structure has been developed and synthesized on Xilinx FPGA to verify the flexibility features, hardware requirements and to analyze the performance of the LDPC decoder. Index Terms—Digital communication, error correction codes, flexible structures, cyclic codes, logic design, field programmable gate array I.

Journal of Networks•Mar 1, 2012•12 citations

A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz

A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMax, WLAN and DVB-S2. In addition, different combinations of permuted random sub-matrices are embedded in layers, to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated by using the proposed technique has bit error rate (BER) performance very close to that of unstructured random matrices. A prototype model of partially-parallel decoder architecture has been designed by using the various matrix configurations available in the proposed technique. FPGA design results show that the proposed decoder is resource efficient and the power requirements are comparable to that of ASIC based decoders.

IEEE International Conference on Multimedia and Expo (ICME)•Jul 1, 2011•10 citations
There are many low-density parity-check (LDPC) decoder architectures in the literature most of which are based on structured codes. Besides been specific to a particular class of codes, suggested architectures are limited in scalability. The major challenge in decoder design and implementation is the consideration of several strongly interrelated factors. These factors affect decoder computation and communication complexity, and error-correcting performance. In this paper we present a low-complexity, flexible and scalable LDPC decoder architecture for quasi-cyclic codes that supports multiple code designs (size, weights, rates, regular and irregular). The architecture is a result of a combination of flexible code construction and computation overlapping techniques. The architecture is based on overlapping techniques that allow sequential processing of check and variable nodes. The overlapping techniques lead to a low-complexity decoder interconnect compared to the existing techniques as they allow serial processing of code sub-matrices as compared to parallel processing of all sub-matrices in the existing overlapping technique. Although the architecture is based on quasi-cyclic codes, it can also be applied to random or other structured codes making it the most flexible, scalable and high-throughput partly-parallel LDPC decoder architecture.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
In this paper, we propose a low-complexity entirely-overlapped partially-parallel decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. For a (c, t)-regular QC-LDPC decoder, this decoder can achieve approximate 100% hardware utilization efficiency (HUE) and entirely overlapped decoding by using only one check node process unit group (CNUG) to process c groups of check node messages sequentially. Compared with traditional partially-parallel decoder, the quantities of check node process unit (CNU), barrel shifters and counters can be decreased prominently. Moreover, it is flexible in code rate and code length.
A novel flexible decoding architecture for quasi-cyclic (QC) low-density parity-check (LDPC) code is proposed in this paper to reduce decoding complexity. The novelty of this architecture lies in a new time-sharing scheme of processing units, which provides low complexity and flexible serial factor of decoding hardware. Without loss of coding performance, the architecture requires significantly less processing units compared with known semi-parallel decoders at the expense of throughput decrease, while keeping memory requirement unchanged. As demonstrated by hardware and software implementation results, the proposed architecture is advisable and competent for wireless mobile systems and portable devices.
We introduce a flexible layered decoder architecture for Quasi-Cyclic Low Density Parity Check (LDPC) codes. An iterative construction of the parity check matrix is exploited by the proposed decoder to achieve various degrees of parallelism, characterized by a high utilization of variable and check processing nodes, absence of memory conflicts, and a simple and scalable interconnection network. Furthermore, the proposed LDPC decoder supports variable code rate, information-word length and order of modulation. A comparison to prior-art decoders proves the efficiency of the proposed scheme.
Abstract—Hardware implementation of partially-parallel Low-Density Parity-Check (LDPC) decoders using unstructured random matrices is very complex and requires huge hardware resources. To alleviate the complexity and minimize resource requirements, structured LDPC matrices are used. This paper presents a novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) structured matrix for LDPC decoder. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMAX, WLAN and DVB-S2. In addition, different combinations of permuted sub-matrices are inserted in layers at different levels of matrix hierarchy to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated using the proposed technique have a marginal loss of less than 0.1 dB at a bit error rate (BER) performance 10-5 compared to unstructured random matrices. A hardware model of the proposed matrix structure has been developed and synthesized on Xilinx FPGA to verify the flexibility features, hardware requirements and to analyze the performance of the LDPC decoder. Index Terms—Digital communication, error correction codes, flexible structures, cyclic codes, logic design, field programmable gate array I.
A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMax, WLAN and DVB-S2. In addition, different combinations of permuted random sub-matrices are embedded in layers, to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated by using the proposed technique has bit error rate (BER) performance very close to that of unstructured random matrices. A prototype model of partially-parallel decoder architecture has been designed by using the various matrix configurations available in the proposed technique. FPGA design results show that the proposed decoder is resource efficient and the power requirements are comparable to that of ASIC based decoders.