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International Conference on Advanced Communication Technology

Low-complexity entirely-overlapped parallel decoder architecture for quasi-cyclic LDPC codes

Weizhi Lu, Piming Ma

Published Feb 15, 2009• 0 citations
OpenAlex

Abstract

In this paper, we propose a low-complexity entirely-overlapped partially-parallel decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. For a (c, t)-regular QC-LDPC decoder, this decoder can achieve approximate 100% hardware utilization efficiency (HUE) and entirely overlapped decoding by using only one check node process unit group (CNUG) to process c groups of check node messages sequentially. Compared with traditional partially-parallel decoder, the quantities of check node process unit (CNU), barrel shifters and counters can be decreased prominently. Moreover, it is flexible in code rate and code length.

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IEEE International Conference on Communication Systems (ICCS)•Nov 1, 2008•2 citations
In this paper, we propose a low-complexity entirely-overlapped partially-parallel decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. For a (c, t)-regular QC-LDPC decoder, this decoder can achieve approximate 100% hardware utilization efficiency (HUE) and entirely overlapped decoding by using only one check node process unit group (CNUG) to process c groups of check node messages sequentially. Compared with traditional partially-parallel decoder, the quantities of check node process unit (CNU), barrel shifters and counters can be decreased prominently. Moreover, it is flexible in code rate and code length.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
There are many low-density parity-check (LDPC) decoder architectures in the literature most of which are based on structured codes. Besides been specific to a particular class of codes, suggested architectures are limited in scalability. The major challenge in decoder design and implementation is the consideration of several strongly interrelated factors. These factors affect decoder computation and communication complexity, and error-correcting performance. In this paper we present a low-complexity, flexible and scalable LDPC decoder architecture for quasi-cyclic codes that supports multiple code designs (size, weights, rates, regular and irregular). The architecture is a result of a combination of flexible code construction and computation overlapping techniques. The architecture is based on overlapping techniques that allow sequential processing of check and variable nodes. The overlapping techniques lead to a low-complexity decoder interconnect compared to the existing techniques as they allow serial processing of code sub-matrices as compared to parallel processing of all sub-matrices in the existing overlapping technique. Although the architecture is based on quasi-cyclic codes, it can also be applied to random or other structured codes making it the most flexible, scalable and high-throughput partly-parallel LDPC decoder architecture.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. For the first time, this paper proposes a partial-parallel decoder architecture based on the Min-max algorithm for quasi-cyclic NB-LDPC codes. A novel boundary tracking based scheme and corresponding architecture are developed to implement the elementary step of the check node processing. In addition, layered decoding is applied, and the hardware units are optimized to reduce the latency and area. This paper also introduces an overlapped method for the check node processing among different layers to further speed up the decoding. From complexity analysis, the proposed decoder with 5 iterations for a (837,726) code over GF(25) can easily achieve 60 Mbps throughput on ASIC devices. It is 40% more efficient than prior designs.
In this paper, an area efficient partially parallel decoder architecture suited for (modified) min-sum decoding algorithm for general high rate quasi-cyclic low-density parity-check (QC-LDPC) codes is proposed. To reduce the hardware complexity for parallel processing, an efficient data scheduling unit is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Typically, over 30% of memory can be saved with the architecture presented in this paper. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems.
Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE.
A novel flexible decoding architecture for quasi-cyclic (QC) low-density parity-check (LDPC) code is proposed in this paper to reduce decoding complexity. The novelty of this architecture lies in a new time-sharing scheme of processing units, which provides low complexity and flexible serial factor of decoding hardware. Without loss of coding performance, the architecture requires significantly less processing units compared with known semi-parallel decoders at the expense of throughput decrease, while keeping memory requirement unchanged. As demonstrated by hardware and software implementation results, the proposed architecture is advisable and competent for wireless mobile systems and portable devices.