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Communications technology

New Min-Sum Decoding Algorithm for π-rotation LDPC Codes

Zijian Dong

Published Jan 1, 2009• 0 citations
OpenAlex

Abstract

π-rotation LDPC codes have many advantages [6] ,such as simple encoding structure,less memory requirement,easy circuit implementation. This paper proposes a new efficient encoding algorithm and a new Min-Sum decoding algorithm for the π-rotation LDPC codes based on the row index matrix and column index matrix of parity check matrix H. Those encoding/decoding algorithms are simple,or even demands no construction of need to construct the real parity check matrix.

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π-rotation LDPC codes have many advantages [6] ,such as simple encoding structure,less memory requirement,easy circuit implementation. This paper proposes a new efficient encoding algorithm and a new Min-Sum decoding algorithm for the π-rotation LDPC codes based on the row index matrix and column index matrix of parity check matrix H. Those encoding/decoding algorithms are simple,or even demands no construction of need to construct the real parity check matrix.
π-rotation LDPC codes are characterized by their simple encoding structure,little memory requirement and easy circuit implementation.A new regular encoding structure for π-rotation LDPC codes is provided,whose parity check matrix His described by a few indexes and the number of which is less than the code length.This encoding structure is also easy to adjust code rate and code length.A new simple but efficient encoding scheme is also given to encode codeword with the aid of the indexes.Two-dimension arrays are used to store the belief information between check nodes and variable nodes,and then the BP Algorithm is developed.Simulation results indicate that these codes perform as well as regular low-density parity check codes based on completely random matrix constructions.
The original low-density parity-check (LDPC) codes were developed by Robert Gallager in early 1960 and are based on a random parity-check matrix construction. In the mid 1990's it was discovered that LDPC codes could be modified slightly to provide the more powerful error correction. These newer LDPC codes, based on an irregular column weight in the underlying check matrix, were still defined with random construction techniques. The Pi-rotation LDPC codes discovered by Echard are a family of LDPC codes completely defined by a small set of integers and have several symmetrical features that are exploited to build efficient encoding and decoding designs. The Pi-rotation codes can be extended to include irregular matrix patterns to obtain the highest performance. In this dissertation we develop a heuristic algorithm to find the best parity-check matrix for Pi-rotation LDPC codes.
This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. For one check node update of normalized min-sum algorithm, if the current row weight is dc, dcmultiplications are needed. If dcis large, dcmultiplications are needed, which leads to high complexity. In this article, one innovative method for check node update has been found, which can obviously reduce the number of multiplication operations for the normalized min-sum algorithm and the number of comparison/selection operations for the row weight matched min-sum algorithm of high rate LDPC codes. Simulations have claimed the performance of normalized min-sum and row weight matched min-sum is nearly the same as that of Log-BP, namely the optimal algorithm, which has shown that normalized min-sum and row weight matched min-sum are good choices for LDPC.
The high encoding complexity of LDPC codes can be solved by designing structured parity-check matrix. If the parity-check matrix of LDPC codes is composed of same type of blocks, decoder implementation can be simple, this structure allow structured decoding and required memory for storing the parity-check matrix can be reduced largely. In this paper, we propose a construction algorithm for short block length structured LDPC codes based on girth condition, PEG algorithm and variable node connectivity. The code designed by this algorithm shows similar performance to other codes without structured constraint in low SNR and better performance in high SNR than those by simulation
This paper presents a look-up table based, configurable and serial-parallel scheduled π-rotation LDPC decoder. By using the proposed permutation mapping scheme together with an optimized normalized min-sum decoding algorithm, the LDPC decoder structure and circuit resource requirements can be greatly reduced. Furthermore, the proposed approach is compatible with different code lengths, bit widths and permutation vectors provided that the parity-check matrix has the π-rotation structure. Specifically, the proposed architecture in this work is implemented with a code length of 1968, a code rate of 1/2, 6-bit quantization and an iteration limit of 10 on a Xilinx Virtex4 XC4VLS200 FPGA. The synthesis results demonstrate the feasibility of the proposed approach to achieve a good BER-SNR performance using a simple decoding scheme and an efficient circuit implementation.
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.