The original low-density parity-check (LDPC) codes were developed by Robert Gallager in early 1960 and are based on a random parity-check matrix construction. In the mid 1990's it was discovered that LDPC codes could be modified slightly to provide the more powerful error correction. These newer LDPC codes, based on an irregular column weight in the underlying check matrix, were still defined with random construction techniques. The Pi-rotation LDPC codes discovered by Echard are a family of LDPC codes completely defined by a small set of integers and have several symmetrical features that are exploited to build efficient encoding and decoding designs. The Pi-rotation codes can be extended to include irregular matrix patterns to obtain the highest performance. In this dissertation we develop a heuristic algorithm to find the best parity-check matrix for Pi-rotation LDPC codes.
The original low-density parity-check (LDPC) codes were developed by Robert Gallager in early 1960 and are based on a random parity-check matrix construction. In the mid 1990's it was discovered that LDPC codes could be modified slightly to provide the more powerful error correction. These newer LDPC codes, based on an irregular column weight in the underlying check matrix, were still defined with random construction techniques. The Pi-rotation LDPC codes discovered by Echard are a family of LDPC codes completely defined by a small set of integers and have several symmetrical features that are exploited to build efficient encoding and decoding designs. The Pi-rotation codes can be extended to include irregular matrix patterns to obtain the highest performance. In this dissertation we develop a heuristic algorithm to find the best parity-check matrix for Pi-rotation LDPC codes.
We introduce an ensemble of quasi-regular low-density parity check error control codes we call /spl pi/-rotation LDPC codes. These codes are completely defined by a single permutation vector of length n/8 where n is the length of the code. We present an efficient encoding scheme and circuit design based on the single permutation. Simulation results indicate that these codes perform as well as regular low density parity check codes based on completely random matrix constructions. These features make the /spl pi/-rotation code valuable for practical communication system implementation.
π-rotation LDPC codes are characterized by their simple encoding structure,little memory requirement and easy circuit implementation.A new regular encoding structure for π-rotation LDPC codes is provided,whose parity check matrix His described by a few indexes and the number of which is less than the code length.This encoding structure is also easy to adjust code rate and code length.A new simple but efficient encoding scheme is also given to encode codeword with the aid of the indexes.Two-dimension arrays are used to store the belief information between check nodes and variable nodes,and then the BP Algorithm is developed.Simulation results indicate that these codes perform as well as regular low-density parity check codes based on completely random matrix constructions.
There is an important breakthrough in the field of forward error correction techniques, low-density parity-check (LDPC) codes. These codes have potential to approach the Shannon limit with reliable performance on a given channel, known as the channel capacity. Recently, researchers pay much more attention towards LDPC codes because its performance is better than Turbo codes. However, the LDPC code is the best when it is an irregular code and uses with a very large block-length. Although, the short block-length LDPC codes perform not so well, they are easy to implement in various practical applications. Therefore, there is still a demand of new development on the encoding side of LDPC codes for various ranges of code rate and code length so as to capable of using in many applications.This thesis proposes the development of quasi-cyclic (QC) LDPC codes for column weight 3. In the first part of this thesis, we propose a new construction algorithm of QC-LDPC codes for medium to large block-length by combining QC-LDPC codes of small block-length as their component codes, via Chinese remainder theorem (CRT). Such component codes were constructed by permuting each column block sequentially to attain the desire local girth. After combining all component codes to generate an expanded parity-check matrix, the resulting girth is greater than or at least equal to the maximum girth of the component codes. Simulation results show that our proposed construction method of the parity-check matrix significantly outperforms the other well-known existing methods in terms of low error-floor, simple structure, high performance, and can reduce encoding complexity.In addition, this thesis also proposes two new construction methods for QC-LDPC codes, namely a base matrix method and a subtraction based method. A base matrix based method is a simple, less computational complexity method for constructing the exponent matrix (3, K) of girth 8, 10 and 12 of QC-LDPC codes. Another method is a subtraction method, which has a similar exponent matrix as a base matrix method and has a girth at least 8. Results indicate that the LDPC codes constructed from these two methods have flexibility for arbitrary block-column length K and have a similar BER performance if compared to existing methods.
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.
Low-density parity-check (LDPC) codes are a class of linear block codes with implementable decoders, which provide near-capacity performance on a large set of data-transmission and data-storage channels. LDPC codes were invented by Gallager in his 1960 doctoral dissertation and were mostly ignored during the 35 years that followed. One notable exception is the important work of Tanner in 1981, in which Tanner generalized LDPC codes and introduced a graphical representation of LDPC codes, now called a Tanner graph. The study of LDPC codes was resurrected in the mid 1990s with the work of MacKay, Luby, and others [3–6], who noticed, apparently independently of Gallager's work, the advantages of linear block codes with sparse (low-density) parity-check matrices. This chapter introduces LDPC codes and creates a foundation for further study of LDPC codes in later chapters. We start with the fundamental representations of LDPC codes via parity-check matrices and Tanner graphs. We then learn about the decoding advantages of linear codes that possess sparse parity-check matrices. We will see that this sparseness characteristic makes the code amenable to various iterative decoding algorithms, which in many instances provide near optimal performance. Gallager of course recognized the decoding advantages of such low-density parity-check codes and he proposed a decoding algorithm for the BI-AWGNC and a few others for the BSC. These algorithms have received much scrutiny in the past decade, and are still being studied.