In this article we present a fully programmable and scalable partly-parallel LDPC decoder architecture together with an optimum mapping and scheduling algorithm. The proposed algorithm exploits the full parallelism of the architecture at any time for any code, which means that the mapping algorithm achieves 100% utilization of the architecture. The proposed design is fully programmable and can be reconfigured for a different LDPC code by changing the initialization of the control memory. Thus the architecture can be used for a multi-standard decoder which supports decoding of any structured or unstructured LDPC code. Furthermore, the parallelism of the architecture is unconstrained and fully scalable which allows to exchange hardware cost and throughput with fine granularity. In contrast to previously proposed programmable designs our approach uses parallel variable and check node processing and thus doubles the data throughput.
In this article we present a fully programmable and scalable partly-parallel LDPC decoder architecture together with an optimum mapping and scheduling algorithm. The proposed algorithm exploits the full parallelism of the architecture at any time for any code, which means that the mapping algorithm achieves 100% utilization of the architecture. The proposed design is fully programmable and can be reconfigured for a different LDPC code by changing the initialization of the control memory. Thus the architecture can be used for a multi-standard decoder which supports decoding of any structured or unstructured LDPC code. Furthermore, the parallelism of the architecture is unconstrained and fully scalable which allows to exchange hardware cost and throughput with fine granularity. In contrast to previously proposed programmable designs our approach uses parallel variable and check node processing and thus doubles the data throughput.
In recent years, the amount of digital data which is stored and transmitted for private and public usage has increased considerably. To allow a save transmission and storage of data despite of error-prone transmission media, error correcting codes are used. A large variety of codes has been developed, and in the past decade low-density parity-check (LDPC) codes which have an excellent error correction performance became more and more popular. Today, low-density parity-check codes have been adopted for several standards, and efficient decoder hardware architectures are known for the chosen structured codes. However, the existing decoder designs lack flexibility as only few structured codes can be decoded with one decoder chip. In consequence, different codes require a redesign of the decoder, and few solutions exist for decoding of codes which are not quasi-cyclic or which are unstructured. In this thesis, three different approaches are presented for the implementation of fully programmable LDPC decoders which can decode arbitrary LDPC codes. As a design study, the first programmable decoder which uses a heuristic mapping algorithm is realized on a field-programmable gate array (FPGA), and error correction curves are measured to verify the correct functionality. The main contribution of this thesis lies in the development of the second and the third architecture and an appropriate mapping algorithm. The proposed fully programmable decoder architectures use one-phase message passing and layered decoding and can decode arbitrary LDPC codes using an optimum mapping and scheduling algorithm. The presented programmable architectures are in fact generalized decoder architectures from which the known decoder architectures for structured LDPC codes can be derived.
This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.
The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units (PUs) and complex interconnections. A practical solution of area-efficient decoders is to use the partially parallel architecture in which a PU is shared for several rows or columns. It is important in the partially parallel architecture to determine the rows or columns to be processed in a PU and their processing order. The dependencies between rows and columns should be considered to minimize the overall processing time by overlapping the decoding operations. This paper proposes an efficient scheduling algorithm that can be applied to general LDPC codes, which is based on the concept of matrix permutation. Experimental results show that the proposed scheduling achieves a higher decoding rate, leading to a reduction of 25% processing time on average. A 1024-bit rate-1/2 LDPC decoder, employing the proposed scheduling algorithm, provides almost 1 Gbps decoding throughput and occupies one-fifth the area compared to the fully parallel decoder.
In this paper, an area efficient partially parallel decoder architecture suited for (modified) min-sum decoding algorithm for general high rate quasi-cyclic low-density parity-check (QC-LDPC) codes is proposed. To reduce the hardware complexity for parallel processing, an efficient data scheduling unit is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Typically, over 30% of memory can be saved with the architecture presented in this paper. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
This paper proposes a flexible low-density parity-check (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput. LDPC codes are widely adopted by the new emerging standards for wireless communication systems and storage applications due to their near-capacity error correcting performance. To achieve high decoding throughput on GPU, we leverage the parallelism embedded in the check-node computation and variable-node computation and propose a parallel strategy of partitioning the decoding jobs among multi-processors in GPU. In addition, we propose a scalable multi-codeword decoding scheme to fully utilize the computation resources of GPU. Furthermore, we developed a novel adaptive performance-tuning method to make our decoder implementation more flexible and scalable. The experimental results show that our LDPC decoder is scalable and flexible, and the adaptive performance-tuning method can deliver the peak performance based on the GPU architecture.