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Asilomar Conference on Signals, Systems and Computers (ACSSC)

GPU accelerated scalable parallel decoding of LDPC codes

Guohui Wang, Michael Wu, Yang Sun, Joseph R. Cavallaro

Published Nov 1, 2011• 23 citations
Publisher

Abstract

This paper proposes a flexible low-density parity-check (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput. LDPC codes are widely adopted by the new emerging standards for wireless communication systems and storage applications due to their near-capacity error correcting performance. To achieve high decoding throughput on GPU, we leverage the parallelism embedded in the check-node computation and variable-node computation and propose a parallel strategy of partitioning the decoding jobs among multi-processors in GPU. In addition, we propose a scalable multi-codeword decoding scheme to fully utilize the computation resources of GPU. Furthermore, we developed a novel adaptive performance-tuning method to make our decoder implementation more flexible and scalable. The experimental results show that our LDPC decoder is scalable and flexible, and the adaptive performance-tuning method can deliver the peak performance based on the GPU architecture.

DOI
10.1109/acssc.2011.6190388

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This paper proposes a flexible low-density parity-check (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput. LDPC codes are widely adopted by the new emerging standards for wireless communication systems and storage applications due to their near-capacity error correcting performance. To achieve high decoding throughput on GPU, we leverage the parallelism embedded in the check-node computation and variable-node computation and propose a parallel strategy of partitioning the decoding jobs among multi-processors in GPU. In addition, we propose a scalable multi-codeword decoding scheme to fully utilize the computation resources of GPU. Furthermore, we developed a novel adaptive performance-tuning method to make our decoder implementation more flexible and scalable. The experimental results show that our LDPC decoder is scalable and flexible, and the adaptive performance-tuning method can deliver the peak performance based on the GPU architecture.
Non-binary low-density parity-check (LDPC) codes have been shown to attain near capacity error correcting performance in noisy wireless communication channels. It is well known that these codes require a very large number of operations per-bit to decode. This high computational complexity along with a parallel decoder structure makes graphics processing units (GPUs) an attractive platform for acceleration of the decoding algorithm. The seemingly random memory access patterns associated with decoding are generally beneficial to error-correcting performance but present a challenge to designers who want to leverage the computational capabilities of the GPU. In this paper we describe the design of an efficient decoder implementation based on GPUs and a corresponding set of powerful non-binary LDPC codes. Using the belief propagation algorithm with a sequential message updating scheme it is shown that we are able to exploit parallelism inherent in the decoding algorithm while decreasing the number of decoding iterations required for convergence.
To meet the high throughput requirement of communication systems, the design of high-throughput low-density parity-check (LDPC) decoders has attracted significant attention. This paper proposes a high-throughput GPU-based LDPC decoder, aiming at the large-scale data process scenario, which optimizes the decoder from the perspectives of the decoding parallelism and data scheduling strategy, respectively. For decoding parallelism, the intra-codeword parallelism is fully exploited by combining the characteristics of the flooding-based decoding algorithm and GPU programming model, and the inter-codeword parallelism is improved using the single-instruction multiple-data (SIMD) instructions. For the data scheduling strategy, the utilization of off-chip memory is optimized to satisfy the demands of large-scale data processing. The experimental results demonstrate that the decoder achieves 10 Gbps throughput by incorporating the early termination mechanism on general-purpose GPU (GPGPU) devices and can also achieve a high-throughput and high-power-efficiency performance on low-power embedded GPU (EGPU) devices. Compared with the state-of-the-art work, the proposed decoder had a ×1.787 normalized throughput speedup at the same error correcting performance.
In this letter, we present design and implementation of a parallel software low-density parity-check (LDPC) decoding algorithm on graphics processing units (GPUs). As a solution for the LDPC decoder, dedicated application-specific integrated circuit or field programmable gate array implementations is proposed in recent years in order to support high throughput despite their long deployment cycle, high design, and especially fixed functionalities. On the other hand, the implementations on GPU as a software solution provide flexible, scalable, and less expensive solutions in a shorter deployment cycle. We present some GPU-based optimizations for a major LDPC decoder algorithm to obtain high throughput in digital communication systems. Experimental results demonstrate that the proposed LDPC decoder achieves more than 1.27 Gb/s peak throughput on a single GPU.
As powerful error correcting codes, Low-Density Parity-Check (LDPC) codes have been adopted as a fundamental building block by dirty paper coding (DPC), which indicates that lossless precoding is theoretically possible at any signal-to-noise ratio (SNR), and is a promising strategy in future communication systems. However, to achieve this performance gain demands huge computation complexity. For its lower cost and better flexibility, the GPU-based LDPC decoder is an emerging research subject. Based on the perspective of GPU hardware architecture, a multi-stage optimizing mapping strategy (MSOMS) is proposed and implemented to accelerate LDPC decoding. The performance is boosted significantly by balancing the memory access and computation load, optimizing execution configuration and the memory access pattern, and fully utilizing the on-chip high speed resources. Proposed decoders can achieve 383-and 442-speedup compared to CPU-based decoder for LDPC and RA code (another ensemble of LDCP code), and the achieved throughput is comparable to existed GPU-based decoders, which confirm the efficiency of the MSOMS strategy.
Modern active and passive satellite and airborne sensors with higher temporal, spectral and spatial resolutions for Earth remote sensing result in a significant increase in data volume. This poses a challenge for data transmission over error-prone wireless links to a ground receiving station. Low-density parity-check (LDPC) codes have been adopted in modern communication systems for robust error correction. Demands for LDPC decoders at a ground receiving station for efficient and flexible data communication links have inspired the usage of a cost-effective high-performance computing device. In this paper we propose a graphic-processing-unit (GPU)-based regular LDPC decoders with the log sum-product iterative decoding algorithm (log-SPA). The GPU code was written to run NVIDIA GPUs using the compute unified device architecture (CUDA) language with a novel implementation of asynchronous data transfer for LDPC decoding. Experimental results showed that the proposed GPU-based high-throughput regular LDPC decoder achieved a significant 271x speedup compared to its CPU-based single-threaded counterpart written in the C language.