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IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

An Optimizing Strategy Research of LDPC Decoding Based on GPGPU

Luechao Yuan, Zuocheng Xing, Yang Zhang, Xiaobao Chen

Published Jul 1, 2013• 1 citation
Publisher

Abstract

As powerful error correcting codes, Low-Density Parity-Check (LDPC) codes have been adopted as a fundamental building block by dirty paper coding (DPC), which indicates that lossless precoding is theoretically possible at any signal-to-noise ratio (SNR), and is a promising strategy in future communication systems. However, to achieve this performance gain demands huge computation complexity. For its lower cost and better flexibility, the GPU-based LDPC decoder is an emerging research subject. Based on the perspective of GPU hardware architecture, a multi-stage optimizing mapping strategy (MSOMS) is proposed and implemented to accelerate LDPC decoding. The performance is boosted significantly by balancing the memory access and computation load, optimizing execution configuration and the memory access pattern, and fully utilizing the on-chip high speed resources. Proposed decoders can achieve 383-and 442-speedup compared to CPU-based decoder for LDPC and RA code (another ensemble of LDCP code), and the achieved throughput is comparable to existed GPU-based decoders, which confirm the efficiency of the MSOMS strategy.

DOI
10.1109/trustcom.2013.233

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As powerful error correcting codes, Low-Density Parity-Check (LDPC) codes have been adopted as a fundamental building block by dirty paper coding (DPC), which indicates that lossless precoding is theoretically possible at any signal-to-noise ratio (SNR), and is a promising strategy in future communication systems. However, to achieve this performance gain demands huge computation complexity. For its lower cost and better flexibility, the GPU-based LDPC decoder is an emerging research subject. Based on the perspective of GPU hardware architecture, a multi-stage optimizing mapping strategy (MSOMS) is proposed and implemented to accelerate LDPC decoding. The performance is boosted significantly by balancing the memory access and computation load, optimizing execution configuration and the memory access pattern, and fully utilizing the on-chip high speed resources. Proposed decoders can achieve 383-and 442-speedup compared to CPU-based decoder for LDPC and RA code (another ensemble of LDCP code), and the achieved throughput is comparable to existed GPU-based decoders, which confirm the efficiency of the MSOMS strategy.
To meet the high throughput requirement of communication systems, the design of high-throughput low-density parity-check (LDPC) decoders has attracted significant attention. This paper proposes a high-throughput GPU-based LDPC decoder, aiming at the large-scale data process scenario, which optimizes the decoder from the perspectives of the decoding parallelism and data scheduling strategy, respectively. For decoding parallelism, the intra-codeword parallelism is fully exploited by combining the characteristics of the flooding-based decoding algorithm and GPU programming model, and the inter-codeword parallelism is improved using the single-instruction multiple-data (SIMD) instructions. For the data scheduling strategy, the utilization of off-chip memory is optimized to satisfy the demands of large-scale data processing. The experimental results demonstrate that the decoder achieves 10 Gbps throughput by incorporating the early termination mechanism on general-purpose GPU (GPGPU) devices and can also achieve a high-throughput and high-power-efficiency performance on low-power embedded GPU (EGPU) devices. Compared with the state-of-the-art work, the proposed decoder had a ×1.787 normalized throughput speedup at the same error correcting performance.
This paper proposes a flexible low-density parity-check (LDPC) decoder which leverages graphic processor units (GPU) to provide high decoding throughput. LDPC codes are widely adopted by the new emerging standards for wireless communication systems and storage applications due to their near-capacity error correcting performance. To achieve high decoding throughput on GPU, we leverage the parallelism embedded in the check-node computation and variable-node computation and propose a parallel strategy of partitioning the decoding jobs among multi-processors in GPU. In addition, we propose a scalable multi-codeword decoding scheme to fully utilize the computation resources of GPU. Furthermore, we developed a novel adaptive performance-tuning method to make our decoder implementation more flexible and scalable. The experimental results show that our LDPC decoder is scalable and flexible, and the adaptive performance-tuning method can deliver the peak performance based on the GPU architecture.
Low-Density Parity-Check (LDPC) code is a powerful error correcting code. It has been widely adopted by many communication systems. Finding a fast and efficient design of LDPC has been an active research area. This paper proposes a high performance design for irregular LDPC decoding on a general purpose graphic processing unit (GPGPU). A GPGPU is a many-core architecture which enables massively parallel computing. In this paper, a high degree of computation parallelism has been exposed by decoding multiple LDPC code-words concurrently. An innovative data structure is proposed to more efficiently leverage memory coalescing for the irregular data accesses of LDPC decoding. Data spatial locality is maximized by keeping more reusable data within the on-chip cache of a GPGPU. The data communication overhead between a host and a GPGPU is minimized through a single word copy for the convergence check. The experiment results show that the proposed design can achieve up to 55.68X runtime improvement, when compared with a sequential LDPC program on a CPU.
Low density parity check (LDPC) decoding process is known as compute intensive. This kind of digital communication applications was recently implemented onto graphic processing unit (GPU) devices for LDPC code performance estimation and/or for real-time measurements. Overall previous studies about LDPC decoding on GPU were based on the implementation of the flooding-based decoding algorithm that provides massive computation parallelism. More efficient layered schedules were proposed in literature because decoder iteration can be split into sublayer iterations. These schedules seem to badly fit onto GPU devices due to restricted computation parallelism and complex memory access patterns. However, the layered schedules enable the decoding convergence to speed up by two. In this letter, we show that: 1) layered schedule can be efficiently implemented onto a GPU device; and 2) this approach—implemented onto a low-cost GPU device—provides higher throughputs with identical correction performances (BER) compared to previously published results.
We consider flexible decoder implementation of low density parity check (LDPC) codes via compute-unified-device-architecture (CUDA) programming on graphics processing unit (GPU), a research subject of considerable recent interest. An important issue in LDPC decoder design based on CUDA-GPU is realizing coalesced memory access, a technique that reduces memory transaction time considerably. In previous works along this direction, it has not been possible to achieve coalesced memory access in both the read and write operations due to the asymmetric nature of the bipartite graph describing the LDPC code structure. In this paper, a new algorithm is proposed that enables coalesced memory access in both the read and write operations for one half of the decoding process - either the bit-to-check or the check-to-bit message passing. For the remaining half of the decoding step our scheme requires address transformation in both the read and write operations but one translating array is sufficient. We also describe the use of on-chip shared memory and texture cache. Overall, experimental results show that proposed GPU-based LDPC decoder achieves more than 234×-speedup compared to CPU-based LDPC decoders and also outperforms existing GPU-based decoders by a significant margin.
The Enhanced Quasi-Maximum Likelihood(EQML) decoder has better decoding performance for short Low Density Parity Check(LDPC) codes than traditional Belief Propagation(BP) decoder,and can meet the high reliability requirements of 5G mobile communication.However,its decoding speed is greatly reduced due to its complex computational structure.To address the problem,this paper proposes a parallel acceleration scheme based on Graphics Processing Unit(GPU) for EQML decoder.The scheme compresses and stores the parity check matrix of irregular LDPC codes,and resorts the traditional BP decoding algorithms to maximize the utilization of threads in Kernel.Then parallel decoding is implemented for multi-code words in each stage of reprocessing,so as to realize memory access optimization and parallel decoding of streams.Experimental results show that the GPU-based EQML decoder improves the speed by two orders of magnitude compared with the CPU-based decoder,while keeping the error correction performance.