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IEEE Transactions on Applied Superconductivity

A Fast Turn-Around Time Process for Fabrication of Qubit Circuits

Vijay Patel, W. Chen, Shawn Pottorf, James E. Lukens

Published Jun 1, 2005• 15 citations
Publisher

Abstract

The authors describe a process for fabrication of Nb/AlO/sub x//Nb Josephson junction circuits for quantum computation. The process involves only one etch step and incorporates electron beam lithography and a self-aligned lift-off of the dielectric resulting in a short turn-around time of 4-5 days. Deep submicron junctions of size down to 0.15 /spl times/ 0.15 /spl mu/m/sup 2/ have been fabricated and tested. Results of junction quality measurements will be presented. In particular, a subgap resistance of /spl sim/1 G/spl Omega/ measured at /spl sim/0.4 K indicates that the junction's subgap leakage should not be a limitation for quantum computation.

DOI
10.1109/tasc.2005.849708

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The authors describe a process for fabrication of Nb/AlO/sub x//Nb Josephson junction circuits for quantum computation. The process involves only one etch step and incorporates electron beam lithography and a self-aligned lift-off of the dielectric resulting in a short turn-around time of 4-5 days. Deep submicron junctions of size down to 0.15 /spl times/ 0.15 /spl mu/m/sup 2/ have been fabricated and tested. Results of junction quality measurements will be presented. In particular, a subgap resistance of /spl sim/1 G/spl Omega/ measured at /spl sim/0.4 K indicates that the junction's subgap leakage should not be a limitation for quantum computation.
Nb/Al–AlO x /Nb tunnel junctions are often used in the studies of macroscopic quantum phenomena and superconducting qubit applications of the Josephson devices. In this work, we describe a convenient and reliable process using electron beam lithography for the fabrication of high-quality, submicron-sized Nb/Al–AlO x /Nb Josephson junctions. The technique follows the well-known selective Nb etching process and produces high-quality junctions with V m = 100 mV at 2.3 K for the typical critical current density of 2.2 kA/cm 2 , which can be adjusted by controlling the oxygen pressure and oxidation time during the formation of the tunnelling barrier. We present the results of the temperature dependence of the sub-gap current and in-plane magnetic-field dependence of the critical current, and compare them with the theoretical predictions.
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Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.
Submicrometer Nb/Al−AlOx/Nb{\rm Nb}/{\rm Al}{-}{\rm AlO}_{\rm x}/{\rm Nb}Nb/Al−AlOx​/Nb Integrated Circuit Fabrication Process for Quantum Computing Applications
We have developed a low Jc(100-1000 A/cm2) submicrometer Nb integrated circuit fabrication process for SQUID-based quantum computing applications. The baseline process consists of 7 masking steps including Pd-Au resistor, Nb/Al-AlOx/Nb trilayer, two Nb wiring layers and two sputtered SiO2dielectric layers. We have also fabricated wafers with an Nb ground plane. Using deep-UV lithography, inductively coupled plasma etch tools, and self-aligned lift-off for device definition, we routinely achieve micrometer lines and spaces with 400 nm minimum junction dimensions. Room temperature testing is used to select wafers in process and junction annealing has been calibrated for trimming current density. We will describe the process which has been used to produce circuits with over 100 junctions.
We have developed a combined photolithography and electron-beam lithography fabrication process for sub-\mum to \mum-size Nb/Al-AlOx/Nb Josephson junctions. In order to define the junction size and protect its top electrode during anodic oxidation, we developed and used the new concept of an aluminum hard mask. Josephson junctions of sizes down to 0.5 \mum2 have been fabricated and thoroughly characterized. We found that they have a very high quality, which is witnessed by the IV curves with quality parameters Vm > 50 mV and Vgap = 2.8 mV at 4.2 K, as well as IcRN products of 1.75-1.93 mV obtained at lower temperatures. In order to test the usability of our fabrication process for superconducting quantum bits, we have also designed, fabricated and experimentally investigated phase qubits made of these junctions. We found a relaxation time of T1 = 26 ns and a dephasing time of T2 = 21 ns.
The objective of our research is to develop a machine-aligned technique for the definition and insulation of Nb/Al-AlO/sub x//Nb superconducting-insulating-superconducting (SIS) tunnel junctions with areas as small as 0.2 /spl mu/m/sup 2/. The fabrication of such ultrasmall area planar SIS junctions had previously only been achieved using electron beam lithography (JPL). Typical techniques for the fabrication of micron-scale SIS junctions involve a self-aligned resist lift-off process. The resist pattern is used to define both the junction counter-electrode and the insulation field that separates the wiring layer from the base electrode. The wiring layer contacts the junction counter-electrode through a via in the insulation field that is created during resist liftoff. In our process, the junction is defined and insulated in separate steps; a via through the insulation layer to the junction is aligned and defined using a gallium focused ion beam with nanometer spot-size. Such small area SIS junctions have potential applications in high frequency SIS mixer circuits. They may also be used in experiments to investigate quantum coherence in superconducting circuits and may even serve as the key elements in future superconducting quantum computers.