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IEEE Transactions on Applied Superconductivity

Direct Measurement of Jitter in a JTL

Y.-K.-K. Fung, Gerald W. Gibson, John F. Bulzacchelli, Stanislav V. Polonsky, M. B. Ketchen

Published Mar 8, 2013• 8 citations
Publisher

Abstract

A direct technique for the measurement of jitter in a Josephson transmission line (JTL), which is similar to an approach used to measure complementary metal-oxide-semiconductor latch metastability, is presented. The experiment yields a one-sigma jitter value of 74 fs per JTL stage in 1 kA/cm2rapid single flux quantum technology. The experimental configuration has been modeled with JSIM, and the result agrees with the experimental data. Additionally, an analytical model has been developed to assess the scaling of the jitter-to-stage delay ratio with critical current density of the Josephson junctions comprising the JTL. Finally, we compare the measured upper bound jitter per stage of a 65-nm complementary metal-oxide-semiconductor inverter chain with that of a 1 kA/cm2JTL.

DOI
10.1109/tasc.2013.2238279

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IEEE Transactions on Applied Superconductivity•Mar 1, 2001•18 citations
A direct technique for the measurement of jitter in a Josephson transmission line (JTL), which is similar to an approach used to measure complementary metal-oxide-semiconductor latch metastability, is presented. The experiment yields a one-sigma jitter value of 74 fs per JTL stage in 1 kA/cm2rapid single flux quantum technology. The experimental configuration has been modeled with JSIM, and the result agrees with the experimental data. Additionally, an analytical model has been developed to assess the scaling of the jitter-to-stage delay ratio with critical current density of the Josephson junctions comprising the JTL. Finally, we compare the measured upper bound jitter per stage of a 65-nm complementary metal-oxide-semiconductor inverter chain with that of a 1 kA/cm2JTL.
We describe the readout process of the state of a Josephson flux qubit via solitons in Josephson transmission lines (JTLs) as they are in use in the standard rapid single flux quantum technology. We consider the situation where the information about the state of the qubit is stored in the time delay of the soliton. We analyze dissipative underdamped JTLs, take into account their jitter, and provide estimates of the measuring time and efficiency of the measurement for relevant experimental parameters.
Timing jitter is an important constraint for the performance of SFQ circuits. We focus on the timing jitter in a Josephson transmission line (JTL) that induces timing errors at logic gates. A proper data analysis of 2-bit shift registers gave a jitter value of about 0.08 ps for a single Josephson junction in a JTL powered at a designed bias current. The variations in timing parameters of logic cells also give rise to timing errors. We experimentally determined the timing parameters in several logic cells and found that the deviations between actual and nominal values are within 2 ps. The relationship between the gray zone and circuit scale was estimated by extrapolating the transition curves observed in 2-bit shift registers. The estimated circuit scale was 20,000-100,000 JJs and 1,000 JJs at an operating clock frequency of 20 GHz and 40 GHz, respectively.
A Josephson transmission line closed to form a ring was used to measure the time jitter produced by a single shunted Josephson junction. A toggle flip-flop cell was connected to a sampling oscilloscope, and was used to detect the flux quantum arrival time. Time jitter was determined from the variation of this time. The jitter was measured as a function of the number of cycles the flux quantum made in the ring. The reduced jitter produced by a single junction of 0.2 ps/spl radic/n (n-number of junctions passed by the quantum) was measured using Hypres 1 kA/cm/sup 2/ chip fabrication technology. It was found that jitter varies the distance between the quanta with the same rate of 0.2 ps/spl radic/n.
We evaluated timing jitter based on a time-to-digital converter (TDC) having sub-pico seconds time resolution. The measured jitter at liquid helium temperature was 65 fs for an optimally damped simple junction composing a conventional Josephson transmission line fabricated with the NEC standard process. The temperature dependence and shunt resistance dependence of jitter indicate that the jitter originates from thermal noise generated at the shunt resistor of the junction. We also found that the timing jitter of a balanced comparator is much larger than that of a JTL. The jitter of a balanced comparator is independent of temperature. This means that the jitter of a balanced comparator does not arise from thermal noise.
We report on the timing jitter characterization of the superconducting single flux quantum (SFQ) coincidence circuit, which is an essential component of the superconducting coincidence photon counter. Two superconducting nanowire single photon detectors (SSPDs), each of which is irradiated with optically time-controlled photons, are connected to the SFQ coincidence circuit, and the timing jitter of the SFQ circuit is evaluated by changing the relative time delay between two input ports for the SFQ comparator unit. We successfully observe the transition curve of the probability of obtaining the signal from the SFQ coincidence circuit by sweeping photon arrival time to each SSPD and confirm that this curve shifts temporally upon changing the bias current to the Josephson transmission line (JTL) in the SFQ circuit. A systematic investigation reveals that the relation between time delay and the bias current to JTL can be estimated. The full width half maximum timing jitter of the SFQ circuit is 1.1 ps, which is sufficiently low so that it does not influence the entire timing jitter of the coincidence photon counter.
Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumption. In this paper, we present two original experiments to demonstrate that it's also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17 GHz, latency of 860 ps and BER of 10/sup -19/ for 3.5 /spl mu/m technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 /spl mu/m technology of TRW, Inc. These figures are in good agreement with our simulations.