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IEEE Transactions on Applied Superconductivity

Time jitter measurement in a circular Josephson transmission line

V. K. Kaplunenko, V. Borzenets

Published Mar 1, 2001• 18 citations
Publisher

Abstract

A Josephson transmission line closed to form a ring was used to measure the time jitter produced by a single shunted Josephson junction. A toggle flip-flop cell was connected to a sampling oscilloscope, and was used to detect the flux quantum arrival time. Time jitter was determined from the variation of this time. The jitter was measured as a function of the number of cycles the flux quantum made in the ring. The reduced jitter produced by a single junction of 0.2 ps/spl radic/n (n-number of junctions passed by the quantum) was measured using Hypres 1 kA/cm/sup 2/ chip fabrication technology. It was found that jitter varies the distance between the quanta with the same rate of 0.2 ps/spl radic/n.

DOI
10.1109/77.919340

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A Josephson transmission line closed to form a ring was used to measure the time jitter produced by a single shunted Josephson junction. A toggle flip-flop cell was connected to a sampling oscilloscope, and was used to detect the flux quantum arrival time. Time jitter was determined from the variation of this time. The jitter was measured as a function of the number of cycles the flux quantum made in the ring. The reduced jitter produced by a single junction of 0.2 ps/spl radic/n (n-number of junctions passed by the quantum) was measured using Hypres 1 kA/cm/sup 2/ chip fabrication technology. It was found that jitter varies the distance between the quanta with the same rate of 0.2 ps/spl radic/n.
Timing jitter is an important factor in determining the limit of speed and scale of single-flux-quantum circuits. We estimated the timing jitter by a simple method using 2-bit shift registers. It was estimated by observing the transition between 1- and 2-mode operations while changing the bias current to the clock line. A sharp transition was observed in the shift register with a smaller number of Josephson junctions in the clock and data lines, suggesting the existence of a finite timing jitter. The timing jitter per Josephson junction was estimated to be 0.09 ps at a designed bias current. The temperature dependence supported that the timing jitter comes from thermal fluctuation.
Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumption. In this paper, we present two original experiments to demonstrate that it's also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17 GHz, latency of 860 ps and BER of 10/sup -19/ for 3.5 /spl mu/m technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 /spl mu/m technology of TRW, Inc. These figures are in good agreement with our simulations.
The authors propose a new type of sampler design based on shunted junctions ( beta c =1). The sampler is to be used for the investigation of single flux quantum devices (RSFQ) employing similar junctions (Kaplunenko et al. 1989, Filippenko et al. 1991). They measure the time resolution of the sampler and delay time of the shunted Josephson junction array. The circuit was manufactured on a single chip and was DC powered. They employed Nb-AlO x -Nb tunnel junctions of 300 A m -2 critical current density and observed Josephson oscillations of the output junction at frequencies from 6 to 50 GHz. Despite a long plasma period of 20 ps the time resolution was 5 ps. The transmission line of 27 Josephson junctions (critical current 165 mu A each) demonstrated time delay of 0.5 ps mu A -1 .
We experimentally evaluated random number sequences generated by a superconducting hardware random number generator composed of a Josephson-junction oscillator, a rapid-single-flux-quantum (RSFQ) toggle flip-flop (TFF), and an RSFQ AND gate. Test circuits were fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. Measurements were conducted in a liquid helium bath. The random numbers were generated for a trigger frequency of 500 kHz under the oscillating Josephson-junction at 29 GHz. 26 random number sequences of 20 kb length were evaluated for bias voltages between 2.0 and 2.7 mV. The NIST FIPS PUBS 140-2 tests were used for the evaluation. 100% pass rates were confirmed at the bias voltages of 2.5 and 2.6 mV. We found that the Monobit test limited the pass rates. As numerical simulations suggested, a detailed evaluation for the probability of obtaining “1” demonstrated the monotonical dependence on the bias voltage.
We evaluated timing jitter based on a time-to-digital converter (TDC) having sub-pico seconds time resolution. The measured jitter at liquid helium temperature was 65 fs for an optimally damped simple junction composing a conventional Josephson transmission line fabricated with the NEC standard process. The temperature dependence and shunt resistance dependence of jitter indicate that the jitter originates from thermal noise generated at the shunt resistor of the junction. We also found that the timing jitter of a balanced comparator is much larger than that of a JTL. The jitter of a balanced comparator is independent of temperature. This means that the jitter of a balanced comparator does not arise from thermal noise.
Timing jitter is an important constraint for the performance of SFQ circuits. We focus on the timing jitter in a Josephson transmission line (JTL) that induces timing errors at logic gates. A proper data analysis of 2-bit shift registers gave a jitter value of about 0.08 ps for a single Josephson junction in a JTL powered at a designed bias current. The variations in timing parameters of logic cells also give rise to timing errors. We experimentally determined the timing parameters in several logic cells and found that the deviations between actual and nominal values are within 2 ps. The relationship between the gray zone and circuit scale was estimated by extrapolating the transition curves observed in 2-bit shift registers. The estimated circuit scale was 20,000-100,000 JJs and 1,000 JJs at an operating clock frequency of 20 GHz and 40 GHz, respectively.