Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEICE Transactions on Electronics

Evaluation of a True Random Number Generator Utilizing Timing Jitters in RSFQ Logic Circuits

Kenta SATO, Naonori Sega, Yuta Somei, Hiroshi Shimada, Takeshi Onomi, Yoshinao Mizugaki

Published Jan 18, 2022• 5 citations
Publisher

Abstract

We experimentally evaluated random number sequences generated by a superconducting hardware random number generator composed of a Josephson-junction oscillator, a rapid-single-flux-quantum (RSFQ) toggle flip-flop (TFF), and an RSFQ AND gate. Test circuits were fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. Measurements were conducted in a liquid helium bath. The random numbers were generated for a trigger frequency of 500 kHz under the oscillating Josephson-junction at 29 GHz. 26 random number sequences of 20 kb length were evaluated for bias voltages between 2.0 and 2.7 mV. The NIST FIPS PUBS 140-2 tests were used for the evaluation. 100% pass rates were confirmed at the bias voltages of 2.5 and 2.6 mV. We found that the Monobit test limited the pass rates. As numerical simulations suggested, a detailed evaluation for the probability of obtaining “1” demonstrated the monotonical dependence on the bias voltage.

DOI
10.1587/transele.2021ses0001

Related papers

Random Number Generation Utilizing Timing Jitters of Single-Flux-Quantum Propagation

Yoshinao Mizugaki, Kenta Sato, Hiroshi Shimada +1 more

We present superconducting hardware random number generators comprising single-flux-quantum (SFQ) digital circuits. We refer to them as SFQ oscillator-based hardware random number generators, or SO-HRNGs in short. The source of randomness in SO-HRNGs is timing jitters induced by thermal noises in integrated circuits. Test circuits were fabricated using a 10 kA/cm2Nb/AlOx/Nb integration process, and measured in a liquid helium bath. The NIST FIPS 140-2 test suite was used for evaluation of the randomness of generated random numbers. For a single-output SO-HRNG, pass rates of 100% were confirmed. For a triple-output SO- HRNG, on the other hand, pass rates for two outputs reached 100%, whereas those for the rest were not as high as 100%, 76% at the highest.

Photonics & Electromagnetics Research Symposium (PIERS)•Jul 3, 2023•0 citations

Evaluation of True Random Number Sequences Generated by Utilizing Timing Jitters in Superconducting Integrated Circuits

Kenta Sato, Naonori Sega, Hiroshi Shimada +1 more

Abstract A Hardware Random Number Generator (HRNG), which generates true random number sequences, is studied. In superconducting Single Flux Quantum (SFQ) circuitry, HRNGs that utilized timing jitters in trigger signals have been demonstrated. In this paper, we propose an HRNG with two oscillators to enhance stability against variation of oscillator frequencies. We investigate the characteristics of random numbers generated with the proposed HRNG not only by numerical simulation but also by experiments using Nb test circuits. In the numerical simulation, the probability of “1” in random number sequences has a local minimum of “1” output probability at conditions where fclk (the clock oscillator frequency) and fgate (the gate oscillator frequency) are approximately equal (fclk ≈ fgate ) for fclk ≤ 60 GHz. It is also found that pass rates for the FIPS140-2 random number tests are little affected by variations of fclk at fgate = 69.2 GHz. The random number generation rate for fclk = 60 GHz and fgate = 43 GHz reaches 3.98 GHz. In experimental measurements, random numbers of 1 Mbits generated by a test circuit pass the SP800-22 random number tests at fclk = 48.79 GHz and fgate = 19.81 GHz.

Journal of Physics Conference Series•Jul 1, 2023•1 citation

Operation of RSFQ Hardware Random Number Generator Comprising Two Josephson Oscillators

Yoshinao Mizugaki, Kenta SATO, Hiroshi Shimada

We describe the operation of a rapid-single-flux-quantum (RSFQ) hardware random number generator comprising two Josephson oscillators, an XOR gate, and a non-destructive read-out (NDRO) cell. Single-flux-quantum (SFQ) pulse trains fed to the input terminals of the XOR gate contain timing jitters due to thermal noises. Then, the output of the XOR gate becomes random, which is stored in the NDRO cell and fetched by the trigger signal. We experimentally evaluated the output randomness of a test circuit fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. For evaluation, the NIST FIPS 140-2 test suite was used. 24 random number sequences of 20 kb length were acquired with the trigger signal of 1 MHz, and evaluated for each operation condition. Relationships between the output randomness and operation conditions were obtained. In addition, numerical simulation demonstrated true random number generation at 20 GHz.

IEICE Transactions on Electronics•Nov 19, 2024•0 citations

Hardware Random Number Generator Using Josephson Oscillation and SFQ Logic Circuits

Takeshi Onomi, Yoshinao Mizugaki

A hardware random number generator using Josephson oscillation and a few single flux quantum (SFQ) logic gates is presented. The logic circuit of the random number generator consists of one toggle flip flop and one and gate. A prototype random number generator is designed by logic cells based on a 2.5-kA/cm2Nb/AlOx/Nb integration process. The fundamental operation at a few hundred megahertz of the random number sampling frequency is confirmed by numerical simulation when a DC/SFQ converter is used for generating trigger signals. An additional delay line using an overdamped Josephson transmission line is used for increasing the timing jitter to get random numbers. The delay line makes it possible for the random number generator to operate over 1 GHz. To confirm the fundamental operation of the circuit, a primitive SFQ random number generator is fabricated using the AIST standard process with 2.5-kA/cm2Nb/AlOx/Nb junctions and the standard logic cell library. A random number generation based on a low-speed functional test is successfully confirmed.

IEEE Transactions on Applied Superconductivity•May 4, 2020•11 citations

Hardware random number generator with a complementary structure using Josephson oscillation and SFQ logic circuits

Takeshi Onomi, Shogo Yoshida

Abstract A hardware true random number generator with a complementary structure using Josephson oscillation and SFQ logic circuits is proposed. The proposed structure consists of independent two random number generators which are an original one and another one with inverted outputs. This structure decreases shifting from the ideal ratio of binary numbers simply. The difference of the generation ratio of binary random numbers is compensated by interleaved two random number sequences. A designed random number generator is fabricated using a 10-kA/cm2 Nb/AlOx/Nb junction integration technology. Experimental low-speed test results show random number generations with the low bias voltage dependence of the ratio of binary numbers.

Journal of Physics Conference Series•Jul 1, 2025•0 citations

Three Parallel Generation of a 4-bit M-Sequence Using Single-Flux-Quantum Digital Circuits

Yoshinao Mizugaki, Yasuaki Mutoh, Yoshiaki Urai +2 more

Maximum-length sequences (M-sequences) are known as pseudo-random numbers generated with relatively simple digital circuits. In this paper, we present a single-flux-quantum digital circuit that generated three output bits of a 4-bit M-sequence in one clock operation. The circuit comprised three clocked exclusive-or gates, one delay flip-flop, three dc/SFQ converters (for set, reset, and low-frequency clock signals), and three SFQ/dc converters (for three parallel outputs), all of which were integrated on a superconducting Nb chip. A 10-GHz clock generator was also implemented for high-speed testing. The total number of Nb/AlOx/Nb Josephson junctions was 568. Verilog simulation demonstrated correct circuit operation with a 20-GHz clock, which corresponded to the generation rate of 60 Gb/s. The measurement was carried out in a liquid helium bath. Low-speed testing with a 1-kHz clock demonstrated periodic signals of three parallelized 4-bit M-sequence. We also confirmed that the outputs were correctly shifted when 13 clock signals of 10 GHz were fed between two 1-kHz clock signals.

IEEE Transactions on Applied Superconductivity•Mar 1, 2016•3 citations
We experimentally evaluated random number sequences generated by a superconducting hardware random number generator composed of a Josephson-junction oscillator, a rapid-single-flux-quantum (RSFQ) toggle flip-flop (TFF), and an RSFQ AND gate. Test circuits were fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. Measurements were conducted in a liquid helium bath. The random numbers were generated for a trigger frequency of 500 kHz under the oscillating Josephson-junction at 29 GHz. 26 random number sequences of 20 kb length were evaluated for bias voltages between 2.0 and 2.7 mV. The NIST FIPS PUBS 140-2 tests were used for the evaluation. 100% pass rates were confirmed at the bias voltages of 2.5 and 2.6 mV. We found that the Monobit test limited the pass rates. As numerical simulations suggested, a detailed evaluation for the probability of obtaining “1” demonstrated the monotonical dependence on the bias voltage.
We present superconducting hardware random number generators comprising single-flux-quantum (SFQ) digital circuits. We refer to them as SFQ oscillator-based hardware random number generators, or SO-HRNGs in short. The source of randomness in SO-HRNGs is timing jitters induced by thermal noises in integrated circuits. Test circuits were fabricated using a 10 kA/cm2Nb/AlOx/Nb integration process, and measured in a liquid helium bath. The NIST FIPS 140-2 test suite was used for evaluation of the randomness of generated random numbers. For a single-output SO-HRNG, pass rates of 100% were confirmed. For a triple-output SO- HRNG, on the other hand, pass rates for two outputs reached 100%, whereas those for the rest were not as high as 100%, 76% at the highest.
Abstract A Hardware Random Number Generator (HRNG), which generates true random number sequences, is studied. In superconducting Single Flux Quantum (SFQ) circuitry, HRNGs that utilized timing jitters in trigger signals have been demonstrated. In this paper, we propose an HRNG with two oscillators to enhance stability against variation of oscillator frequencies. We investigate the characteristics of random numbers generated with the proposed HRNG not only by numerical simulation but also by experiments using Nb test circuits. In the numerical simulation, the probability of “1” in random number sequences has a local minimum of “1” output probability at conditions where fclk (the clock oscillator frequency) and fgate (the gate oscillator frequency) are approximately equal (fclk ≈ fgate ) for fclk ≤ 60 GHz. It is also found that pass rates for the FIPS140-2 random number tests are little affected by variations of fclk at fgate = 69.2 GHz. The random number generation rate for fclk = 60 GHz and fgate = 43 GHz reaches 3.98 GHz. In experimental measurements, random numbers of 1 Mbits generated by a test circuit pass the SP800-22 random number tests at fclk = 48.79 GHz and fgate = 19.81 GHz.
We describe the operation of a rapid-single-flux-quantum (RSFQ) hardware random number generator comprising two Josephson oscillators, an XOR gate, and a non-destructive read-out (NDRO) cell. Single-flux-quantum (SFQ) pulse trains fed to the input terminals of the XOR gate contain timing jitters due to thermal noises. Then, the output of the XOR gate becomes random, which is stored in the NDRO cell and fetched by the trigger signal. We experimentally evaluated the output randomness of a test circuit fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. For evaluation, the NIST FIPS 140-2 test suite was used. 24 random number sequences of 20 kb length were acquired with the trigger signal of 1 MHz, and evaluated for each operation condition. Relationships between the output randomness and operation conditions were obtained. In addition, numerical simulation demonstrated true random number generation at 20 GHz.
A hardware random number generator using Josephson oscillation and a few single flux quantum (SFQ) logic gates is presented. The logic circuit of the random number generator consists of one toggle flip flop and one and gate. A prototype random number generator is designed by logic cells based on a 2.5-kA/cm2Nb/AlOx/Nb integration process. The fundamental operation at a few hundred megahertz of the random number sampling frequency is confirmed by numerical simulation when a DC/SFQ converter is used for generating trigger signals. An additional delay line using an overdamped Josephson transmission line is used for increasing the timing jitter to get random numbers. The delay line makes it possible for the random number generator to operate over 1 GHz. To confirm the fundamental operation of the circuit, a primitive SFQ random number generator is fabricated using the AIST standard process with 2.5-kA/cm2Nb/AlOx/Nb junctions and the standard logic cell library. A random number generation based on a low-speed functional test is successfully confirmed.
Abstract A hardware true random number generator with a complementary structure using Josephson oscillation and SFQ logic circuits is proposed. The proposed structure consists of independent two random number generators which are an original one and another one with inverted outputs. This structure decreases shifting from the ideal ratio of binary numbers simply. The difference of the generation ratio of binary random numbers is compensated by interleaved two random number sequences. A designed random number generator is fabricated using a 10-kA/cm2 Nb/AlOx/Nb junction integration technology. Experimental low-speed test results show random number generations with the low bias voltage dependence of the ratio of binary numbers.
Maximum-length sequences (M-sequences) are known as pseudo-random numbers generated with relatively simple digital circuits. In this paper, we present a single-flux-quantum digital circuit that generated three output bits of a 4-bit M-sequence in one clock operation. The circuit comprised three clocked exclusive-or gates, one delay flip-flop, three dc/SFQ converters (for set, reset, and low-frequency clock signals), and three SFQ/dc converters (for three parallel outputs), all of which were integrated on a superconducting Nb chip. A 10-GHz clock generator was also implemented for high-speed testing. The total number of Nb/AlOx/Nb Josephson junctions was 568. Verilog simulation demonstrated correct circuit operation with a 20-GHz clock, which corresponded to the generation rate of 60 Gb/s. The measurement was carried out in a liquid helium bath. Low-speed testing with a 1-kHz clock demonstrated periodic signals of three parallelized 4-bit M-sequence. We also confirmed that the outputs were correctly shifted when 13 clock signals of 10 GHz were fed between two 1-kHz clock signals.