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Journal of Applied Physics

Model for a Josephson sampling gate

Bart J. Van Zeghbroeck

Published Apr 1, 1985• 11 citations
Publisher

Abstract

A simple model for the Josephson sampling gate is presented. The sampler response was calculated analytically for a step-function signal. Two tradeoffs were found: one between time resolution and overshoot and another between time resolution and sensitivity. The model also explains a prepulse in the sampling gate response.
DOI
10.1063/1.335448

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IEEE Transactions on Magnetics•Mar 1, 1985•5 citations
The dynamical behavior of a balance sampling gate, consisting of two directly serially connected Josephson junctions and a common shunt resistor, has been investigated by numerical simulations and approximated equations of the resistive shunted junction model. A reduced damping parameter has been found which determines the sampler behavior alone and enables an optimization. A 2.4-ps rise time of the response to a step-function signal predicted by the approximated theory has been verified by numerical simulations. The sampling gate can be driven directly by a room-temperature generator with a rise time of a few hundred picoseconds.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10\%--90\% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10\%--90\% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.
The time resolution of a Josephson junction sampler depends on the switching time of the junction. This switching time depends on the junctions' plasma frequency and McCumber parameter, but also on the amount of overdrive current applied. An approximate closed form expression is derived for the switching time as a function of the overdrive, excluding damping or noise. A key result is that the switching time depends logarithmically on the overdrive. Numeric simulations are used to justify the approximations made and reveal the dependence on damping. Comparisons are made between the analytic expression and a numeric simulation of the switching time. Application of the results to a Josephson sampler is presented.
A Josephson sampler with direct resistive coupling between sampling gate and sampling pulse generator has been designed and simulated. The sampling gate and the sampling pulse generator comprise two Josephson junction interferometers. A short sampling pulse of 3ps width is generated at a suitable vortex to vortex transition. Delays up to 200ps between the sampling pulse and the main trigger input could be generated with an electronically adjustable circuit on the same chip. A layout of the complete sampling circuit, i.e. the sampling gate, the sampling pulse generator and the electronic delay circuit on a single 36mm2chip has been achieved for the Nb-NbxOy-PbInAu technology. The minimum line width is 8μm. Forj_{\max} = 3kA/cm2a time resolution of 3.5ps is predicted.