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Japanese Journal of Applied Physics

A Direct Coupled Josephson Sampler

Hiroshi Akoh, Shigeki Sakai, Akihiko Yagi, Hisao Hayakawa

Published Jul 1, 1983• 25 citations
Publisher

Abstract

A direct coupled Josephson sampler with a single junction as a sampling gate which is directly connected with a sampler pulser and unknown signal sources by resistors is reported. Devices are fabricated by a Pb-alloy technology with a minimum size of 2.5×2.5 µm2 and a current density of 4 kA/cm2 for junctions. The sampler reconstructs a latching waveform with a 10 ps rise time from an interferometer within a few µA current sensitivity.

DOI
10.1143/jjap.22.l435

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Journal of Applied Physics•May 1, 1986•1 citation
A direct coupled Josephson sampler with a single junction as a sampling gate which is directly connected with a sampler pulser and unknown signal sources by resistors is reported. Devices are fabricated by a Pb-alloy technology with a minimum size of 2.5×2.5 µm2 and a current density of 4 kA/cm2 for junctions. The sampler reconstructs a latching waveform with a 10 ps rise time from an interferometer within a few µA current sensitivity.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler that balances the highest sampler bandwidth (shortest 10%-90% rise time) with minimal sampled waveform distortion. We explore the impacts on the performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations, we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time [or full width at half maximum (FWHM)] as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results, we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and an impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique, the system is fully digital and automated, and the operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%-90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear system analysis of sampled waveforms indicates a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this-as high as 600 GHz.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10\%--90\% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10\%--90\% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.
A high-resolution Josephson sampler using a single fluxoid is fabricated. The sampling pulse generator comprised a two-junction interferometer (DC–SQUID) with a damping resistance resistively coupled to a single junction as the sampling gate to reduce a turn-on delay. An ultra-fast sampling pulse was generated at a vortex-to-vortex transition in this sampler. The fabricated sampler had less than a 5ps time resolution and about a 5 µA current sensitivity. The dynamic waveform associated with two kinds of transitions was observed by the use of this sampler: a vortex-to-vortex transition and a vortex-to-voltage transition. The results show that the pulse corresponding to a single fluxoid has a nearly constant pulse height that is independent of the bias current and that setting the bias current near the critical point results in the long rise time of a DC–SQUID.
A Josephson sampler with direct resistive coupling between sampling gate and sampling pulse generator has been designed and simulated. The sampling gate and the sampling pulse generator comprise two Josephson junction interferometers. A short sampling pulse of 3ps width is generated at a suitable vortex to vortex transition. Delays up to 200ps between the sampling pulse and the main trigger input could be generated with an electronically adjustable circuit on the same chip. A layout of the complete sampling circuit, i.e. the sampling gate, the sampling pulse generator and the electronic delay circuit on a single 36mm2chip has been achieved for the Nb-NbxOy-PbInAu technology. The minimum line width is 8μm. Forj_{\max} = 3kA/cm2a time resolution of 3.5ps is predicted.
The authors propose a new type of sampler design based on shunted junctions ( beta c =1). The sampler is to be used for the investigation of single flux quantum devices (RSFQ) employing similar junctions (Kaplunenko et al. 1989, Filippenko et al. 1991). They measure the time resolution of the sampler and delay time of the shunted Josephson junction array. The circuit was manufactured on a single chip and was DC powered. They employed Nb-AlO x -Nb tunnel junctions of 300 A m -2 critical current density and observed Josephson oscillations of the output junction at frequencies from 6 to 50 GHz. Despite a long plasma period of 20 ps the time resolution was 5 ps. The transmission line of 27 Josephson junctions (critical current 165 mu A each) demonstrated time delay of 0.5 ps mu A -1 .
A novel current-injection Josephson latch with a single-flux quantum memory is experimentally verified. The experimental latch is fabricated by 5-μm Pb-alloy technology and occupies an area of 270×175 μm2, achieving one order of magnitude area reduction compared to magnetically coupled latch. In low-frequency experiments, the proper operation of a single latch under arbitrary input conditions and the proper data transfer from latch to latch are observed. In high-speed experiments, the proper operation of a single latch with cycle time down to 3.7 ns is observed, which is limited by the high-speed restriction of the test instruments at room temperature. These results show the possibility that the complete current injection logic system can be constructed by combining the present latch and current-injection logic gates.