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arXiv:2503.20022

Picosecond Josephson Samplers: Modeling and Measurements

Logan A. Howe, Bart van Zeghbroeck, David I. Olaya, John Biesecker, Charles J. Burroughs, Samuel P. Benz, P. F. Hopkins

Published Mar 25, 2025• 0 citations
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Abstract

Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10\%--90\% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10\%--90\% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.

DOI
10.48550/arxiv.2503.20022

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Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10%--90% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%--90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler that balances the highest sampler bandwidth (shortest 10%-90% rise time) with minimal sampled waveform distortion. We explore the impacts on the performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations, we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time [or full width at half maximum (FWHM)] as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results, we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and an impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique, the system is fully digital and automated, and the operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%-90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear system analysis of sampled waveforms indicates a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this-as high as 600 GHz.
HYPRES, Inc. has introduced to the commercial marketplace a Sampling Oscilloscope/Time Domain Reflectometer (TDR) based on Josephson junction technology. The unit offers measurement performance commensurate with the inherent high speed of the Josephson elements, e.g., bandwidths in excess of 70 GHz and rise times on the order of 5 ps. A Josephson {rigger recognizer and delay circuit allows triggering of the sampling oscilloscope from the signal itself, with full view of the trigger point. Input modules offering different sensitivities or TDR capability are quickly interchangeable, and operating temperature is achieved in less than one minute. The technical details of the cooling technique and the chip circuitry will be described in this paper .
This paper reviews our progress on the high-T c superconducting (HTS) sampler development, covering from the circuit design to the latest experimental data in the sinusoidal and pulse waveform measurements. A computer simulation has revealed that our sampler circuit with an improved design enables waveform measurement with the bandwidth over 100 GHz even with the thermal noise at around 40 K. Using the HTS sampler circuits fabricated employing an improved layout, we demonstrated waveform measurements for sinusoidal signals with frequencies of up to 50 GHz, the upper limit of the signal generator we used, both in the voltage-input-type system with a high-frequency input line and in the current-input-type one with a superconducting pickup coil. In the pulse measurement using an on-chip sampler, we succeeded in observing pico-second-order-wide single flux quantum (SFQ) current pulses, suggesting the potential bandwidth of our HTS sampler of more than 125 GHz.
A Josephson sampler with direct resistive coupling between sampling gate and sampling pulse generator has been designed and simulated. The sampling gate and the sampling pulse generator comprise two Josephson junction interferometers. A short sampling pulse of 3ps width is generated at a suitable vortex to vortex transition. Delays up to 200ps between the sampling pulse and the main trigger input could be generated with an electronically adjustable circuit on the same chip. A layout of the complete sampling circuit, i.e. the sampling gate, the sampling pulse generator and the electronic delay circuit on a single 36mm2chip has been achieved for the Nb-NbxOy-PbInAu technology. The minimum line width is 8μm. Forj_{\max} = 3kA/cm2a time resolution of 3.5ps is predicted.
The dynamical behavior of a balance sampling gate, consisting of two directly serially connected Josephson junctions and a common shunt resistor, has been investigated by numerical simulations and approximated equations of the resistive shunted junction model. A reduced damping parameter has been found which determines the sampler behavior alone and enables an optimization. A 2.4-ps rise time of the response to a step-function signal predicted by the approximated theory has been verified by numerical simulations. The sampling gate can be driven directly by a room-temperature generator with a rise time of a few hundred picoseconds.