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Journal of Applied Physics

Theoretical investigations on the dynamical behavior of a Josephson sampling gate with a balance comparator

Stefan H. Heinemann, Vasili K. Semenov

Published Sep 1, 1987• 1 citation
Publisher

Abstract

The dynamical behavior of a balance sampling gate, consisting of two directly serially connected Josephson junctions and a common shunt resistor, has been investigated by numerical simulations and approximated equations of the resistive shunted junction model. A reduced damping parameter has been found which determines the sampler behavior alone and enables an optimization. A 2.4-ps rise time of the response to a step-function signal predicted by the approximated theory has been verified by numerical simulations. The sampling gate can be driven directly by a room-temperature generator with a rise time of a few hundred picoseconds.

DOI
10.1063/1.339507

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IEEE Transactions on Magnetics•Mar 1, 1985•5 citations
The dynamical behavior of a balance sampling gate, consisting of two directly serially connected Josephson junctions and a common shunt resistor, has been investigated by numerical simulations and approximated equations of the resistive shunted junction model. A reduced damping parameter has been found which determines the sampler behavior alone and enables an optimization. A 2.4-ps rise time of the response to a step-function signal predicted by the approximated theory has been verified by numerical simulations. The sampling gate can be driven directly by a room-temperature generator with a rise time of a few hundred picoseconds.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10\%--90\% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10\%--90\% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.
The dynamic threshold characteristics of Josephson-junction circuits operated as fast signal detectors have been simulated for a wide range of load conditions, pulse widths, and pulse amplitudes. The simulations have been carried out using the familiar resistively and capacitively shunted junction model and a modified version of an approximate Werthamer model for the Josephson junctions. Approximation formulas for the dynamic threshold characteristics are given, and a readout circuitry for inductively shunted sampling gates is presented.>
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler that balances the highest sampler bandwidth (shortest 10%-90% rise time) with minimal sampled waveform distortion. We explore the impacts on the performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations, we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time [or full width at half maximum (FWHM)] as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results, we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and an impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique, the system is fully digital and automated, and the operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%-90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear system analysis of sampled waveforms indicates a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this-as high as 600 GHz.
The authors propose a new type of sampler design based on shunted junctions ( beta c =1). The sampler is to be used for the investigation of single flux quantum devices (RSFQ) employing similar junctions (Kaplunenko et al. 1989, Filippenko et al. 1991). They measure the time resolution of the sampler and delay time of the shunted Josephson junction array. The circuit was manufactured on a single chip and was DC powered. They employed Nb-AlO x -Nb tunnel junctions of 300 A m -2 critical current density and observed Josephson oscillations of the output junction at frequencies from 6 to 50 GHz. Despite a long plasma period of 20 ps the time resolution was 5 ps. The transmission line of 27 Josephson junctions (critical current 165 mu A each) demonstrated time delay of 0.5 ps mu A -1 .
A Josephson sampler with direct resistive coupling between sampling gate and sampling pulse generator has been designed and simulated. The sampling gate and the sampling pulse generator comprise two Josephson junction interferometers. A short sampling pulse of 3ps width is generated at a suitable vortex to vortex transition. Delays up to 200ps between the sampling pulse and the main trigger input could be generated with an electronically adjustable circuit on the same chip. A layout of the complete sampling circuit, i.e. the sampling gate, the sampling pulse generator and the electronic delay circuit on a single 36mm2chip has been achieved for the Nb-NbxOy-PbInAu technology. The minimum line width is 8μm. Forj_{\max} = 3kA/cm2a time resolution of 3.5ps is predicted.