Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

A NRZ-output amplifier for RSFQ circuits

R. Koch, P. Ostertag, E. Crocoll, Martin Götz, M. Neuhaus, Theo Andreas Scherer, M. Winter, W. Jutzi

Published Jun 1, 1999• 9 citations
Publisher

Abstract

Interfaces between RSFQ circuits in the Return-to-Zero (RZ) and semiconductor circuits in the Non-Return-to-Zero (NRZ) mode are developed for data transmission at about 10 GHz clock frequencies reducing the errors owing to a finite sampling jitter of conventional room temperature equipment. A prototype of a NRZ output interface with the Nb-Al/sub 2/O/sub 3/-Nb technology has been simulated, implemented and successfully tested at 100 MHz. The interface can easily be combined with a superconducting pulse amplifier for NRZ output signals in the range of several mV. Corresponding simulations and a layout of the amplifier are presented.

DOI
10.1109/77.783796

Related papers

CMOS-to-SFQ Interface Circuits for RZ and NRZ Coded Signals Transformation

Siqi Li, Xiaoping Gao, Huanli Liu +4 more

A hybrid computing system employing the superconductor central processing unit and semiconductor memory is a prospective strategy to boost speed and power performance. Aiming to convert coded signals at room temperature to single-flux-quantum (SFQ) logic signals in a cryogenic environment, this article presents two types of CMOS-to-SFQ interface circuits for return-to-zero (RZ) and nonreturn-to-zero (NRZ) coded signals transformation. One can double the data rate (DDR) of bipolar RZ signals, and the other can decode unipolar and polar NRZ signals. In the simulation using parameters of the SIMIT Nb03 process, both the interface circuits have up to 20 GHz sampling frequency, more than ±30% bias current margin, and tolerance toward 20 dB SNR white noise. The DDR interface circuit can generate SFQ pulses at both edges of 1.4–2.6 mA bipolar RZ signal, and the decoding interface circuit can interpret 0.2–0.6 mA unipolar and polar NRZ signal into SFQ pulses. The test circuits have been fabricated under the SIMIT Nb03 6 kA/cm2process. In low-frequency measurement, the DDR interface circuit can convert 1.4–2.4 mA bipolar RZ signal, and the decoding interface circuit can convert 0.25–0.5 mA unipolar and polar NRZ signal with more than ±30% bias current margin. In high-frequency measurement, the DDR interface circuit shows an ability to convert a 3.33 GHz input signal.

IEEE Transactions on Applied Superconductivity•Mar 18, 2024•3 citations

Stacked double-flux-quantum output amplifier

Quentin Herr

A suitable data link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall time and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA/cm/sup 2/ foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of /spl plusmn/21% on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation.

IEEE Transactions on Applied Superconductivity•Jun 1, 2005•27 citations

Josephson output interfaces for RSFQ circuits

Oleg A. Mukhanov, Sergey V. Rylov, Dmitri V. Gaidarenko +2 more

We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•85 citations

High-speed demonstration of an output interface driver for single-flux quantum systems

N. Harada, Akira Yoshida, Naoki Yokoyama

The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.

IEEE Transactions on Applied Superconductivity•Sep 1, 2002•9 citations

Design and development of a cryogenic semiconductor amplifier for interfacing RSFQ circuits at 4.2 K

S. Wünsch, E. Crocoll, M. Schubert +3 more

There is a great deal of interest in amplifiers with extremely high bandwidth, low noise and low power consumption which interface RSFQ circuits with commercial room temperature electronics or amplifying SFQ pulses. In this special application a hybrid amplifier should interface an RSFQ circuitry with a Josephson junction array quantizer chip (JA-Q) at 4.2 K. The input signal for the amplifier is generated by an RSFQ signal generator and the output signal fed-in to a Josephson array quantizer. A voltage gain of about 10 4 with a pattern frequency of 2 GHz for a good transfer of the SFQ pulses is required. Additionally, the JA-Q requires a high output current at low power consumption of the amplifier at the same time. Various hybrid amplifiers based on commercially available p-HEMT transistors in an embedded microwave design were designed and characterized. For the p-HEMT transistor characterization at cryogenic temperatures the biasing settings according to an optimum between voltage gain A V and low power consumption P V were determined. Thus a power consumption of P V = 2 mW and a voltage gain of about A V = 4 per stage were achieved. For a preamplifier and an amplifier concept a number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers and the combination of the amplifiers and the JA-Q at 4.2 K showed their good performance without any disturbances of the quantized voltage steps.

Superconductor Science and Technology•Oct 18, 2007•7 citations

Measurement of Superconductive Voltage Drivers up to 25 Gb/s/ch

Y. Hashimoto, Hideo Suzuki, Shuichi Nagasawa +3 more

We report on demonstrations of a superconductive voltage driver (SVD), which generates non-return-to-zero (NRZ) output with an SFQ pulse input, up to 25 Gb/s/ch. The NRZ SVD consists of a coding logic, splitters, buffers, sixteen RS flip-flops (RSFFs), and DC-biased serially connected sixteen 2-junction SQUIDs. Each SQUID is magnetically coupled to the storage loop of each RSFF. The coding logic generates the true and complement signals of the SVD's input data, and the true and complement signals are split into sixteen with the splitters, amplified with the buffers, and applied to the RSFFs as the set and reset signals, respectively. With this configuration, the SQUIDs generate about 2-mV-high NRZ output voltage. The NRZ SVD was fabricated with our 10-kA/cm2Nb process and measured with our cryocooled system. Eye diagram of the NRZ SVD measured at 25 Gb/s/ch clearly opened, indicating low-bit-error-rate (BER) operation. Measured BER was less than 1times10-13at 20 Gb/s/ch for 27-1 pseudo-random bit sequence input.

IEEE Transactions on Applied Superconductivity•May 27, 2009•10 citations
Interfaces between RSFQ circuits in the Return-to-Zero (RZ) and semiconductor circuits in the Non-Return-to-Zero (NRZ) mode are developed for data transmission at about 10 GHz clock frequencies reducing the errors owing to a finite sampling jitter of conventional room temperature equipment. A prototype of a NRZ output interface with the Nb-Al/sub 2/O/sub 3/-Nb technology has been simulated, implemented and successfully tested at 100 MHz. The interface can easily be combined with a superconducting pulse amplifier for NRZ output signals in the range of several mV. Corresponding simulations and a layout of the amplifier are presented.
A hybrid computing system employing the superconductor central processing unit and semiconductor memory is a prospective strategy to boost speed and power performance. Aiming to convert coded signals at room temperature to single-flux-quantum (SFQ) logic signals in a cryogenic environment, this article presents two types of CMOS-to-SFQ interface circuits for return-to-zero (RZ) and nonreturn-to-zero (NRZ) coded signals transformation. One can double the data rate (DDR) of bipolar RZ signals, and the other can decode unipolar and polar NRZ signals. In the simulation using parameters of the SIMIT Nb03 process, both the interface circuits have up to 20 GHz sampling frequency, more than ±30% bias current margin, and tolerance toward 20 dB SNR white noise. The DDR interface circuit can generate SFQ pulses at both edges of 1.4–2.6 mA bipolar RZ signal, and the decoding interface circuit can interpret 0.2–0.6 mA unipolar and polar NRZ signal into SFQ pulses. The test circuits have been fabricated under the SIMIT Nb03 6 kA/cm2process. In low-frequency measurement, the DDR interface circuit can convert 1.4–2.4 mA bipolar RZ signal, and the decoding interface circuit can convert 0.25–0.5 mA unipolar and polar NRZ signal with more than ±30% bias current margin. In high-frequency measurement, the DDR interface circuit shows an ability to convert a 3.33 GHz input signal.
A suitable data link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall time and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA/cm/sup 2/ foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of /spl plusmn/21% on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation.
We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.
The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.
There is a great deal of interest in amplifiers with extremely high bandwidth, low noise and low power consumption which interface RSFQ circuits with commercial room temperature electronics or amplifying SFQ pulses. In this special application a hybrid amplifier should interface an RSFQ circuitry with a Josephson junction array quantizer chip (JA-Q) at 4.2 K. The input signal for the amplifier is generated by an RSFQ signal generator and the output signal fed-in to a Josephson array quantizer. A voltage gain of about 10 4 with a pattern frequency of 2 GHz for a good transfer of the SFQ pulses is required. Additionally, the JA-Q requires a high output current at low power consumption of the amplifier at the same time. Various hybrid amplifiers based on commercially available p-HEMT transistors in an embedded microwave design were designed and characterized. For the p-HEMT transistor characterization at cryogenic temperatures the biasing settings according to an optimum between voltage gain A V and low power consumption P V were determined. Thus a power consumption of P V = 2 mW and a voltage gain of about A V = 4 per stage were achieved. For a preamplifier and an amplifier concept a number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers and the combination of the amplifiers and the JA-Q at 4.2 K showed their good performance without any disturbances of the quantized voltage steps.
We report on demonstrations of a superconductive voltage driver (SVD), which generates non-return-to-zero (NRZ) output with an SFQ pulse input, up to 25 Gb/s/ch. The NRZ SVD consists of a coding logic, splitters, buffers, sixteen RS flip-flops (RSFFs), and DC-biased serially connected sixteen 2-junction SQUIDs. Each SQUID is magnetically coupled to the storage loop of each RSFF. The coding logic generates the true and complement signals of the SVD's input data, and the true and complement signals are split into sixteen with the splitters, amplified with the buffers, and applied to the RSFFs as the set and reset signals, respectively. With this configuration, the SQUIDs generate about 2-mV-high NRZ output voltage. The NRZ SVD was fabricated with our 10-kA/cm2Nb process and measured with our cryocooled system. Eye diagram of the NRZ SVD measured at 25 Gb/s/ch clearly opened, indicating low-bit-error-rate (BER) operation. Measured BER was less than 1times10-13at 20 Gb/s/ch for 27-1 pseudo-random bit sequence input.